tag: 2.5D

Architecting Interposers
By Brian Bailey - 14 Oct, 2021 - Comments: 0

An interposer performs a similar function as a printed circuit board (PCB), but when the interposer is moved inside a package the impact is significant. Neither legacy PCB nor IC design tools can fully perform the necessary design and analysis tasks. But perhaps even more important, adding an interposer to a design may require organizational changes. Today, leading-edge companies have shown ... » read more

HBM3 Memory: Break Through To Greater Bandwidth
By Rambus - 06 Oct, 2021 - Comments: 0

AI/ML’s demands for greater bandwidth are insatiable driving rapid improvements in every aspect of computing hardware and software. HBM memory is the ideal solution for the high bandwidth requirements of AI/ML training, but it entails additional design considerations given its 2.5D architecture. Now we’re on the verge of a new generation of HBM that will raise memory and capacity to new hei... » read more

Fan-Out And Packaging Challenges
By Mark LaPedus - 06 Oct, 2021 - Comments: 2

Semiconductor Engineering sat down to discuss various IC packaging technologies, wafer-level and panel-level approaches, and the need for new materials with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of globa... » read more

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?
By Dina Medhat - 23 Sep, 2021 - Comments: 0

Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric bre... » read more

Automated ESD Protection Verification For 2.5D And 3D ICs
By Siemens EDA - 22 Sep, 2021 - Comments: 0

While automated flows for ESD protection verification are well-established for 2D ICs, 2.5D and 3D designs present new challenges in both ESD circuit design and verification. Advanced automated ESD verification methodology accurately and effectively evaluates ESD protection in 2.5/3D IC designs. Ensuring correct and consistent ESD protection in 2.5/3D ICs raises the reliability and product life... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects
By Ann Mutschler - 22 Sep, 2021 - Comments: 0

Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

System-In-Package Thrives In The Shadows
By Mark LaPedus - 16 Sep, 2021 - Comments: 0

IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

A New Vision For Memory Chip Design And Verification
By Anand Thiruvengadam - 02 Sep, 2021 - Comments: 0

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

New Approaches For Processor Architectures
By Ed Sperling - 26 Aug, 2021 - Comments: 0

Processor vendors are starting to emphasize microarchitectural improvements and data movement over process node scaling, setting the stage for much bigger performance gains in devices that narrowly target what end users are trying to accomplish. The changes are a recognition that domain specificity, and the ability to adjust or adapt designs to unique workloads, are now the best way to impro... » read more

Inside Intel’s Ambitious Roadmap
By Mark LaPedus and Ed Sperling - 23 Aug, 2021 - Comments: 2

Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

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