tag: 28nm

One-on-One: Naoya Hayashi
By Mark LaPedus - 20 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the current and future challenges in the photomask industry with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP). SE: What are the big challenges for the photomask industry today? Hayashi: There are several challenges. Most of the challenges involve mask complexity. It is also quite difficult to handle the mask data, because it is ... » read more

28nm Powers TSMC Forward (Part Deux)
By Barry Pangrle - 14 Feb, 2014 - Comments: 0

TSMC’s financial results for the 4th Quarter of 2013 and for the full year were announced just a few weeks ago, with TSMC stating it had again achieved record sales and profits. TSMC continues to own the 28nm foundry market. TSMC a year ago stated plans to have 20nm as its next technology node in production in 2014 and it looks to be delivering on this projected claim with the announcement th... » read more

Routing Closure Challenges At 28nm And Below
By Jean-Marie Brunet - 03 Jan, 2014 - Comments: 1

As I described in my last article, the gap between router tech files and signoff rule decks at 28 nm and below is generating some serious impacts on tapeout schedules. The mismatch between the router’s simplified tech file and the complex rules that represent the intricate manufacturing requirements at these leading-edge nodes means designs that come from the router “DRC/DFM-clean” will, ... » read more

Power And Signal Line Electro-migration Design And Reliability Validation Challenges For The 28nm Era
By Various Writers - 06 Dec, 2013 - Comments: 0

Reliability verification is an important aspect in the design and development of an integrated circuit (IC) to help guarantee its continued functionality over years of production use. One critical area of reliability verification is the electro-migration check analysis to ensure that the wires and vias used to connect the various devices in the chip do not fail from years of continuous use. ... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

The Week in Review: System-Level Design
By Ed Sperling - 15 Nov, 2013 - Comments: 0

Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs. Synopsys teamed up with CEVA to improve PPA for CEVA’s... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

Uncertainty, But Not Over Power
By Ed Sperling - 25 Oct, 2013 - Comments: 0

The semiconductor industry has reached a crossroads. Lithography has stalled out, NRE is rising, and chipmakers are torn between choices of when and whether to jump to the next process node—and even more daunting, the next one after that—or whether to take half steps with fan outs, 2.5D, or fully depleted SOI. While chips do continue to tape out, the number of critical choices that need... » read more

Blog Review: Oct. 16
By Ed Sperling - 16 Oct, 2013 - Comments: 0

Cadence’s Richard Goering follows Si2’s move into SPICE modeling following the acquisition of the Compact Model Council. Combining standards groups is a growing trend these days. Mentor’s Colin Walls points to the demise of reset buttons. You can always trip a circuit breaker, and usually turn off a device by pulling out the battery, but a reset button is simpler. Where did they go? ... » read more

Can Mask Data Prep Tools Manage Data Glut?
By Ann Mutschler - 15 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler The trend to reduce critical dimension sizes has in turn increased design file sizes, especially with the addition of optical proximity correction (OPC) steps. This extra data translates to a bigger burden to be processed downstream in the flow on the way to the mask writer. At 28nm, design post-OPC data files sizes reach hundreds of gigabytes. With 20nm and below ... » read more

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