tag: 3D NAND

Will Monolithic 3D DRAM Happen?
By Bryon Moyer - 09 Sep, 2021 - Comments: 1

As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

What’s Ahead For DRAM, NAND?
By Mark LaPedus - 19 Aug, 2021 - Comments: 1

For the last year, the semiconductor industry has been in the midst of a boom cycle. But if you look close enough, there are mixed signals in the market, especially in memory. Still, it’s a banner year for semiconductors. In total, the semiconductor market is expected to grow by 18.1% in 2021, according to Semico Research. That compares to 6.6% growth in 2020, according to Semico. Today... » read more

Micron B47R 3D CTF CuA NAND Die, World’s First 176L (195T)
By Jeongdong Choe - 19 Aug, 2021 - Comments: 0

Micron’s 176L 3D NAND is the world’s first 176L 3D NAND Flash memory. TechInsights just found the 512Gb 176L die (B47R die markings) and quickly viewed its process, structure, and die design. Micron 176L 3D NAND is one of the most groundbreaking technologies to date, and it is especially for the storage application such as data center, 5G, AI, cloud, intelligent edge, and mobile devices. Mi... » read more

Revenue Soars For Semiconductor Equipment Power Subsystems
By John West - 10 Jun, 2021 - Comments: 0

Sales of process power and reactive gas subsystems for semiconductor manufacturing equipment are on track to achieve a compound annual growth rate (CAGR) of 23% between 2016 and 2021 – far outpacing the critical subsystems industry average of 16.4% due to multiple positive factors. Process power and reactive gas subsystems account for approximately 13% of all expenditures on critical subsy... » read more

Untangling 3D NAND: Tilt, Registration, And Misalignment
By Kevin Heidrich - 09 Mar, 2021 - Comments: 0

The multiple demands of 3D NAND to enable yield and performance increase in difficulty at each generation. First generation devices, at 24-32 layer pairs, pushed process tools to extremes, going quickly from 10:1 to 40:1 aspect ratios for today’s 64-96 pair single tier devices. The aspect ratios increased as fast as the manufacturing challenges. To continue bit density scaling, processing imp... » read more

DRAM’s Persistent Threat To Chip Security
By Bryon Moyer - 10 Feb, 2021 - Comments: 0

A well-known DRAM vulnerability called "rowhammer," which allows an assailant to disrupt or take control of a system, continues to haunt the chip industry. Solutions have been tried, and new ones are being proposed, but the potential for a major attack persists. First discovered some five years ago, most of the efforts to eliminate the "rowhammer" threat have done little more than mitigate t... » read more

Monitoring Critical Process Steps In 3D NAND Using Picosecond Ultrasonic Metrology With Both Thickness And Sound Velocity Capabilities
By Onto Innovation - 08 Feb, 2021 - Comments: 0

Amorphous carbon (a-C) based hard masks provide superior etch selectivity, chemical inertness, are mechanically strong, and have been used for etching deep, high aspect ratio features that conventional photoresists cannot withstand. Picosecond Ultrasonic Technology (PULSE Technology) has been widely used in thin metal film metrology because of its unique advantages, such as being a rapid, non-... » read more

3D NAND’s Vertical Scaling Race
By Mark LaPedus - 17 Dec, 2020 - Comments: 1

3D NAND suppliers are accelerating their efforts to move to the next technology nodes in a race against growing competition, but all of these vendors are facing an assortment of new business, manufacturing, and cost challenges. Two suppliers, Micron and SK Hynix, recently leapfrogged the competition and have taken the scaling race lead in 3D NAND. But Samsung and the Kioxia-Western Digital (... » read more

Structural Integrity Of Chips
By Ed Sperling - 23 Nov, 2020 - Comments: 0

A new challenge is on the horizon, and it's one that could have some interesting consequences for chip design — structural integrity. Ever since the introduction of finFETs and 3D NAND, the lines have been blurring between electrical and mechanical engineering. After some initial reports of fins collapsing or breaking, and variable distances between layers, chipmakers figured out how to so... » read more

Bonding Issues For Multi-Chip Packages
By Katherine Derbyshire - 19 Nov, 2020 - Comments: 1

The rising cost and complexity of developing chips at the most advanced nodes is forcing many chipmakers to begin breaking up that chip into multiple parts, not all of which require leading edge nodes. The challenge is how to put those disaggregated pieces back together. When a complex system is integrated monolithically — on a single piece of silicon — the final product is a compromise ... » read more

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