tag: 5nm

EUV Mask Blank Battle Brewing
By Mark LaPedus - 15 Nov, 2018 - Comments: 2

Amid the ramp of extreme ultraviolet (EUV) lithography in the market, suppliers of EUV mask blanks are expanding their production. And a new player—Applied Materials—is looking to enter the market. AGC and Hoya, the two main suppliers of EUV mask blanks, are adding capacity for these critical components that are used for EUV photomasks. A mask blank serves as the substrate for a photomas... » read more

Accelerators Everywhere. Now What?
By Ed Sperling - 08 Nov, 2018 - Comments: 0

It's a good time to be a data scientist, but it's about to become much more challenging for software and hardware engineers. Understanding the different types and how data flows is the next path forward in system design. As the number of sources of data rises, creating exponential spikes in the volume of data, entirely new approaches to computing will be required. The problem is understandi... » read more

Using DSA With EUV
By Ed Sperling - 05 Nov, 2018 - Comments: 1

James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science, looks at how directed self-assembly can be used to supplement EUV at advanced nodes. https://youtu.be/PItF4egHOxc     See other tech talk videos here » read more

CMOS Area Scaling And The Need For High Aspect Ratio Vias
By Coventor - 26 Oct, 2018 - Comments: 0

Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route (PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dime... » read more

Building AI SoCs
By Ed Sperling - 25 Oct, 2018 - Comments: 0

Ron Lowman, strategic marketing manager at Synopsys, looks at where AI is being used and how to develop chips when the algorithms are in a state of almost constant change. That includes what moves to the edge versus the data center, how algorithms are being compressed, and what techniques are being used to speed up these chips and reduce power. https://youtu.be/d32jtdFwpcE    ... » read more

EUV’s Uncertain Future
By Ed Sperling - 18 Oct, 2018 - Comments: 8

The ground appears to be solidifying under EUV. Intel announced this week it is reducing its stake in ASML to less than 3%, the second such move in a year. Apparently ASML no longer needs outside help. According to the company's earnings report, ASML turned in net sales of €2.776 billion, a slight increase over the €2.447 billion (GAAP) the company reported in Q3 and way up over the €... » read more

Can Graphene Be Mass Manufactured?
By Katherine Derbyshire - 18 Oct, 2018 - Comments: 3

Since the isolation of graphene in 2004, the high mobility and unique transport properties of 2-dimensional semiconductors have tantalized physicists and materials scientists. Their in-plane carrier transport and lack of dangling bonds potentially can minimize line/edge scattering and other effects of extreme scaling. While 2-D materials cannot compete with silicon at current device dime... » read more

Why Test Costs Will Increase
By Ed Sperling - 08 Oct, 2018 - Comments: 0

The economics of test are under siege. Long seen as a necessary but rather mundane step in ensuring chip quality, or a way of testing circuitry from the inside while it is still in use, manufacturers and design teams have paid little attention to this part of the design-through-manufacturing flow. But problems have been building for some time in three separate areas, and they could have a b... » read more

Thermal Impact On Reliability At 7/5nm
By Ed Sperling - 28 Sep, 2018 - Comments: 0

Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

EUV Pellicle, Uptime And Resist Issues Continue
By Mark LaPedus - 26 Sep, 2018 - Comments: 0

Extreme ultraviolet (EUV) lithography is moving closer to realization, but several problems involving scanner uptime, photoresists and pellicles need to be resolved before this long-overdue technology is put into full production. Intel, Samsung and TSMC are hoping to insert EUV into production at 7nm and/or 5nm. While the remaining issues don’t necessarily pre-empt using EUV, they do affec... » read more

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