tag: 5nm

DSA Re-Enters Litho Picture
By Mark LaPedus - 15 Mar, 2018 - Comments: 1

By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

Why All Nodes Won’t Work
By Ed Sperling - 08 Mar, 2018 - Comments: 4

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

Tech Talk: On-Chip Variation
By Ed Sperling - 01 Mar, 2018 - Comments: 0

Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more

Tech Talk: 5/3nm Parasitics
By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

New Nodes, Materials, Memories
By Ed Sperling - 15 Feb, 2018 - Comments: 0

Ellie Yieh, vice president and general manager of Advanced Product Technology Development at [getentity id="22817" e_name="Applied Materials"], and head of the company's Maydan Technology Center, sat down with Semiconductor Engineering to talk about challenges, changes and solutions at advanced nodes and with new applications. What follows are excerpts of that conversation. SE: How far can w... » read more

Chip Aging Accelerates
By Ed Sperling - 14 Feb, 2018 - Comments: 1

Reliability is becoming an increasingly important proof point for new chips as they are rolled out in new markets such as automotive, cloud computing and industrial IoT, but actually proving that a chip will function as expected over time is becoming much more difficult. In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed ... » read more

New Thermal Issues Emerge
By Ann Mutschler - 12 Feb, 2018 - Comments: 0

Thermal monitoring is becoming more critical as gate density continues to increase at each new node and as chips are developed for safety critical markets such as automotive. This may sound counterintuitive because the whole point of device scaling is to increase gate density. But at 10/7 and 7/5nm, static current leakage is becoming a bigger issue, raising questions about how long [getkc id... » read more

7/5nm Timing Closure Intensifies
By Ann Mutschler - 25 Jan, 2018 - Comments: 1

Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Nodes Vs. Nodelets
By Mark LaPedus - 22 Jan, 2018 - Comments: 0

Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers. There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or "node-lets" being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm. Node-lets ar... » read more

The Future Of FinFETs
By Ed Sperling - 18 Jan, 2018 - Comments: 0

The number of questions about finFETs is increasing—particularly, how long can they continue to be used before some version of gate-all-around FET is required to replace them. This discussion is confusing in many respects. For one thing, a 7nm finFET for TSMC or Samsung is not the same as a 7nm finFET for Intel or GlobalFoundries. There are a bunch of other nodes being proposed, as well, i... » read more

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