tag: Jasper Design Automation

Tortuga Logic: Hardware Security
By Ed Sperling - 26 May, 2015 - Comments: 0

For the Internet of Things to really get rolling, it has to be bulletproof. And given the number of very high-profile security breaches in recent months, it has a long way to go before consumers or businesses will feel comfortable using any of a new wave of smart devices That concern has prompted a wave of acquisitions from companies such as Intel (McAffee), Cadence (Jasper Design Automation... » read more

And the Winner is…
By Brian Bailey - 18 Dec, 2014 - Comments: 0

Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

Next Bonanza: Security Holes
By Ed Sperling - 07 Jul, 2014 - Comments: 0

Security threats—both real and potential—are beginning to reshape the semiconductor business. These threats are drawing venture capitalists back into the industry as they race for the next big opportunity. They are blurring the lines between software and hardware, as threats grow in complexity at every level of a device and its myriad and sometimes perpetual connections to the outside wo... » read more

The Week In Review: Design
By Ed Sperling - 20 Jun, 2014 - Comments: 0

M&A Cadence completed its acquisition of Jasper Design Automation, using cash and revolving credit to finance the deal. It will explain the impact on 2014 financial results in fiscal 2015. Jasper’s team, led by CEO Kathryn Kranen, will now report to Cadence senior VP Charlie Huang in Cadence’s System & Verification Group. The deal was first announced in April. Tools Coverity un... » read more

Blog Review: June 18
By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

It Takes An Army
By Ed Sperling - 05 Jun, 2014 - Comments: 0

Security has always been a two-way educational process. The bad guys figure out where the weaknesses are, and the good guys figure out how they got in and ways to prevent it. This worked fine for antivirus software in the early days of the PC era, because viruses typically were generalized and the damage they did was rather crude and frequently reversible. Increasingly, however, a deep under... » read more

Easing The Path To Evolution
By Ann Mutschler - 29 May, 2014 - Comments: 1

On the surface, revolutionary changes in EDA seem unlikely due to the risk of replacing costly tools, flows and methodologies. But are they really? The answer depends on whom you ask. For Part One, click here. Risk is a big part of the equation here. “There are always pioneers in an organization and what you need to do is find someone who is willing to take some risk and typically it’s o... » read more

EDA Economics Changing
By Ed Sperling - 22 May, 2014 - Comments: 0

From most perspectives, there has never been a better time to be in the EDA business. Automation tools are in demand as complexity rises, and new companies jumping into the semiconductor business are starting out with commercially available tools rather than developing their own—and taking years, sometimes even decades, to replace them. EDA’s slice of the semiconductor market consistent... » read more

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

Pointing Fingers, Often In The Wrong Direction
By Ed Sperling - 08 May, 2014 - Comments: 0

Every design these days, regardless of whether it’s a processor, an SoC, an ASIC, FPGA or stacked die, relies on a combination of re-used and third-party intellectual property. No company—not even Intel, Apple or Samsung—has the capability of building everything itself within a highly compressed market window. There is a spectrum of IP use and re-use, of course. In some cases, it may i... » read more

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