TSMC Targets N2 Production For 2025


April ended with TSMC’s financial results for the 1st Quarter of 2023 reported on April 20, 2023, and their North American Technology Symposium was held on April 27 at the Santa Clara Convention Center. TSMC’s N3 entered volume production in 4Q 2022 and TSMC’s N2 “nanosheet” technology is on schedule for production in 2025. TSMC’s CEO, C.C. Wei, said during the 1Q conference cal... » read more

New Standards Push Co-Packaged Optics


Co-packaged optics (CPOs) promise five times the bandwidth of pluggable connections, but the new architecture requires multiple changes to accommodate different applications. The Optical Internetworking Forum (OIF) recently published standards for co-packaged optics, which are the photonic industry’s hope for handling today’s faster Ethernet interfaces, as well as increasing speeds and p... » read more

Mechanical Challenges Rise With Heterogeneous Integration


Companies integrating multiple chips or chiplets into a package will need to address structural and other mechanical engineering issues, but gaps in the design tools, new materials and interconnect technologies, and a shortage of expertise are making it difficult to address those issues. Throughout most of the history of the semiconductors, few people outside of foundries worried about struc... » read more

True 3D Is Much Tougher Than 2.5D


Creating real 3D designs is proving to be much more complex and difficult than 2.5D, requiring significant innovation in both technology and tools. While there has been much discussion about 3D designs, there are multiple interpretations about what 3D entails. This is more than just semantics, however, because each packaging option requires different design approaches and technologies. And a... » read more

Tech Forecast: Fab Processes To Watch Through 2040


The massive proliferation of semiconductors in more markets, and more applications within those markets, is expected to propel the industry to more than $1 trillion by 2030. But over the next 17 years, semiconductors will reach well beyond the numbers, changing the way people work, how they communicate, and how they measure and monitor their health and well-being. Chips will be the enabling ... » read more

Week In Review: Auto, Security, Pervasive Computing


Security The Biden administration released a National Cybersecurity Strategy report this week, calling on the tech community to shoulder much more responsibility, placing "responsibility on those within our digital ecosystem that are best positioned to reduce risk and shift the consequences of poor cybersecurity away from the most vulnerable in order to make our digital ecosystem more trustwor... » read more

Re-shoring And Rebuilding The IC Supply Chain


Raj Jammy, chief technologist at MITRE Engenuity and executive director of the Semiconductor Alliance, sat down with Semiconductor Engineering to talk about changes in the supply chain, where and how to leverage different capabilities, and why advanced packaging and manufacturing are so critical to economic security. SE: The global supply chain for semiconductors appears to be splintering. W... » read more

U.S. Opens Funding Applications Under CHIPS Act


The 2022 Chips and Science Act provided $39 billion in federal funding to revitalize the U.S. semiconductor industry. Now, the U.S. Department of Commerce, the oversight branch for the CHIPS Act, has taken the first step in opening up applications for this funding. This initial funding opportunity focuses on applications specifically for projects to “construct, expand, or modernize commerc... » read more

Taming Corner Explosion In Complex Chips


There is a tenuous balance between the number of corners a design team must consider, the cost of analysis, and the margins they insert to deal with them, but that tradeoff is becoming a lot more difficult. If too many corners of a chip are explored, it might never see production. If not enough corners are explored, it could reduce yield. And if too much margin is added, the device may not be c... » read more

Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature


A technical paper titled "Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications" was published by researchers at National Yang Ming Chiao Tung University. Abstract: "The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for ... » read more

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