tag: advanced packaging

The 200mm Equipment Scramble
By Ed Sperling - 23 Aug, 2017 - Comments: 0

An explosion in 200mm demand has set off a frenzied search for used semiconductor manufacturing equipment that can be used at older process nodes. The problem is there is not enough used equipment available, and not all of the new or expanding 200mm fabs can afford to pay the premium for refurbished or new equipment. This may sound like a straightforward supply and demand issue, but behind t... » read more

Tech Talk: Smart Manufacturing
By Ed Sperling - 17 Aug, 2017 - Comments: 0

Tom Salmon, vice president of collaborative technology platforms at SEMI, examines the electronics supply chain and what the industry organization is doing to pull all of the pieces together. https://youtu.be/jWX9mayMaZo Related Stories Smart Manufacturing Gains Momentum Problems remain for legacy infrastructure, but adoption will continue to grow as gaps are identified and plugged. ... » read more

Advanced Packaging Moves To Cars
By Ann Mutschler - 07 Aug, 2017 - Comments: 0

By Ann Steffora Mutschler and Ed Sperling As automotive OEMs come up to speed on electrification of vehicles, each at their own pace, they are starting to embrace novel packaging approaches as a way to differentiate themselves in an increasingly competitive market. Wirebond used to dominate this market, where most of the chips were relatively unsophisticated and product cycles were slow�... » read more

What’s After FinFETs?
By Mark LaPedus - 24 Jul, 2017 - Comments: 3

Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

Is 7nm The Last Major Node?
By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

Implementing High-Density-Advanced Packaging for OSATs And Foundries
By Mentor, a Siemens Business - 12 Jul, 2017 - Comments: 0

HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Advanced Packaging Picks Up Steam
By Jeff Dorsch - 10 Jul, 2017 - Comments: 0

The semiconductor industry’s push toward continued miniaturization and increasing complexity is driving wider adoption of system-in-package (SiP) technology. One of the big benefits of [getkc id="199" kc_name="SiP"] is that it allows more features to be squeezed into ever-smaller form factors, such as wearable gadgets and medical implants. So while the individual chips in this package may ... » read more

Primer On Packaging
By Lam Research - 15 Jun, 2017 - Comments: 0

Ever open the body of your smartphone (perhaps unintentionally) and see small, black rectangles stuck on a circuit board? Those black rectangles are packaged chips. The external chip structure protects the fragile integrated circuits inside, as well as dissipates heat, keeps chips isolated from each other, and, importantly, provides connection to the circuit board and other elements. The manufa... » read more

New BEOL/MOL Breakthroughs?
By Mark LaPedus - 15 Jun, 2017 - Comments: 1

Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Going Vertical?
By Debra Vogler - 15 Jun, 2017 - Comments: 0

The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform dens... » read more

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