Best Practice: Scale-Resolving Simulations In Ansys CFD


While today’s CFD simulations are mainly based on Reynolds-Averaged Navier-Stokes (RANS) turbulence models, it is becoming increasingly clear that certain classes of flows are better covered by models in which all or a part of the turbulence spectrum is resolved in at least a portion of the numerical domain. Such methods are termed Scale-Resolving Simulation (SRS) models in this paper. This r... » read more

Blog Review: Oct. 12


Synopsys' Richard Solomon, Madhumita Sanyal, and Gary Ruggles take a look at the possibilities that CXL 3.0 can bring to a variety of data-driven applications that demand increasingly higher levels of memory capacity, with higher bandwidth, more security, and lower latency. Siemens EDA's Rich Edelman provides some tips for debugging UVM testbenches, such as how to determine what line changed... » read more

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues


Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

EVs Raise Energy, Power, And Thermal IC Design Challenges


The transition to electric vehicles is putting pressure on power grids to produce more energy and on vehicles to use that energy much more efficiently, creating a gargantuan set of challenges that will affect every segment of the automotive world, the infrastructure that supports it, and the chips that are required to make all of this work. From a semiconductor standpoint, improvements in th... » read more

Testing Chips For Security


Supply chains and manufacturing processes are becoming increasingly diverse, making it much harder to validate the security in complex chips. To make matters worse, it can be challenging to justify the time and expense to do so, and there’s little agreement on the ideal metrics and processes involved. Still, this is particularly important as chip architectures evolve from a single chip dev... » read more

Blog Review: Oct. 5


Arm's Andrew Pickard chats with Georgia Tech's Azad Naeemi and Da Eun Shim about an effort to evaluate the benefit of new interconnect materials and wire geometry and determine their impacts at the microprocessor level. Synopsys' Shekhar Kapoor shares highlights from a recent panel exploring the promises, challenges, and realities of 3D IC technology, including the potential of 3D nanosystem... » read more

Chip Industry’s Technical Paper Roundup: Oct. 4


New technical papers added to Semiconductor Engineering’s library this week. [table id=55 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Coming In Hot: Requirements For Successful Thermal Management In 3D-IC


As the speed, density, and capabilities of electronics have all increased, power has become a first order driver in almost all electronic systems. For instance, it’s well recognized that heat is often the number one limiting factor in 3D-IC design. High-speed chips stacked close together in a small housing cause things to heat up fast. One of the most common designer responses to overheating ... » read more

Speeding-Up Thermal Simulations Of Chips With ML


A new technical paper titled "A Thermal Machine Learning Solver For Chip Simulation" was published by researchers at Ansys. Abstract "Thermal analysis provides deeper insights into electronic chips' behavior under different temperature scenarios and enables faster design exploration. However, obtaining detailed and accurate thermal profile on chip is very time-consuming using FEM or CFD. Th... » read more

Blog Review: Sept. 28


Cadence's Paul McLellan shares more highlights from the recent Hot Chips, including some very large chips and accelerators for AI and deep learning, new networks and switches, and mobile and edge processors. Synopsys' Marc Serughetti considers the different use cases for digital twins in automotive and how they can help determine the impact of software on verification, test, and validation a... » read more

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