tag: Barcelona Supercomputing Center

Chip Industry’s Technical Paper Roundup: August 9
By Liz Allan - 09 Aug, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=124 /] More Reading Technical Paper Library home » read more

A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains” was published by researchers at Barcelona Supercomputing Center and Intel. Abstract: "HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) du... » read more

Chip Industry’s Technical Paper Roundup: June 20
By Liz Allan - 20 Jun, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=112 /] » read more

Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH. Abstract: "Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., co... » read more

Chip Industry’s Technical Paper Roundup: Mar. 14
By Linda Christensen - 14 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=86 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

SpGEMM Targeting RISC-V Vector Processors (Barcelona Supercomputing Center)
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A new technical paper titled "Optimization of SpGEMM with Risc-V vector instructions" was published (preprint) by researchers at the Barcelona Supercomputing Center. Abstract "The Sparse GEneral Matrix-Matrix multiplication (SpGEMM) C=A×B is a fundamental routine extensively used in domains like machine learning or graph analytics. Despite its relevance, the efficient execution of SpGEMM ... » read more

Is RISC-V Ready For Supercomputing?
By Brian Bailey - 09 Feb, 2023 - Comments: 0

RISC-V processors, which until several years ago were considered auxiliary processors for specific functions, appear to be garnering support for an entirely different type of role — high-performance computing. This is still at the discussion stage. Questions remain about the software ecosystem, or whether the chips, boards, and systems are reliable enough. And there are both business and t... » read more

Chip Industry’s Technical Paper Roundup: Jan 3
By Linda Christensen - 03 Jan, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=72 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

RISC-V Pushes Into The Mainstream
By Marie C. Baca and Ed Sperling - 21 Dec, 2022 - Comments: 1

RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators and extra processing cores to security applications. These changes are subtle but significant. They point to a growing acceptance that chips or chiplets based on an open-source instruction set ar... » read more

RISC-V decoupled Vector Processing Unit (VPU) For HPC
By Technical Paper Link - 20 Dec, 2022 - Comments: 0

A technical paper titled "Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications" was published by researchers at Barcelona Supercomputing Center, Spain. "The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of ... » read more

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