Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling


A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao Paulo, and Arteris Inc. Abstract: "Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent... » read more

Chip Industry’s Technical Paper Roundup: August 9


New technical papers recently added to Semiconductor Engineering’s library: [table id=124 /] More Reading Technical Paper Library home » read more

A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V


A technical paper titled “Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains” was published by researchers at Barcelona Supercomputing Center and Intel. Abstract: "HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) du... » read more

Chip Industry’s Technical Paper Roundup: June 20


New technical papers added to Semiconductor Engineering’s library this week. [table id=112 /] » read more

Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator


A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH. Abstract: "Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., co... » read more

Chip Industry’s Technical Paper Roundup: Mar. 14


New technical papers recently added to Semiconductor Engineering’s library: [table id=86 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

SpGEMM Targeting RISC-V Vector Processors (Barcelona Supercomputing Center)


A new technical paper titled "Optimization of SpGEMM with Risc-V vector instructions" was published (preprint) by researchers at the Barcelona Supercomputing Center. Abstract "The Sparse GEneral Matrix-Matrix multiplication (SpGEMM) C=A×B is a fundamental routine extensively used in domains like machine learning or graph analytics. Despite its relevance, the efficient execution of SpGEMM ... » read more

Is RISC-V Ready For Supercomputing?


RISC-V processors, which until several years ago were considered auxiliary processors for specific functions, appear to be garnering support for an entirely different type of role — high-performance computing. This is still at the discussion stage. Questions remain about the software ecosystem, or whether the chips, boards, and systems are reliable enough. And there are both business and t... » read more

Chip Industry’s Technical Paper Roundup: Jan 3


New technical papers added to Semiconductor Engineering’s library this week. [table id=72 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

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