tag: Cadence

Chip-Package-Board Issues Grow
By Ann Mutschler - 06 Feb, 2017 - Comments: 0

As systems migrate from a single die in a single package on a board, to multiple dies with multiple packaging options and multiple PCB form factors, it is becoming critical to move system planning, assembly, and optimization much earlier in the design-through-manufacturing flow. This is easier said than done. Multiple tools and operating systems are now used at each phase of the flow, partic... » read more

The Week In Review: Design
By Jesse Allen - 03 Feb, 2017 - Comments: 0

Tools Synopsys announced the latest version of its VCS functional verification solution, which integrates native fine-grained parallelism (FGP) and additional engine optimizations for simulation on existing x86 CPU server configurations. Aldec released the latest version of its requirements lifecycle management solutions for FPGAs/SoCs, adding certification document templates and review c... » read more

Blog Review: Feb. 1
By Jesse Allen - 01 Feb, 2017 - Comments: 0

Synopsys' Anand Thiruvengadam investigates the challenges and tradeoffs that come with different abstraction models and use models in mixed-signal verification. Cadence's Paul McLellan highlights 16 big questions facing autonomous cars, from a presentation by Andreessen-Horowitz's Frank Chen. Mentor's Colin Walls says that when it comes to free stuff, keep an eye out for the real cost. ... » read more

Software Modeling Goes Mainstream
By Ed Sperling - 01 Feb, 2017 - Comments: 0

Software modeling is finally beginning to catch on across a wide swath of chipmakers as they look beyond device scaling to improve performance, lower power, and ratchet up security. Software modeling in the semiconductor industry historically has been associated with hardware-software co-design, which has grown in fits and starts since the late 1990s. The largest chipmakers and systems compa... » read more

The Week In Review: Design
By Jesse Allen - 27 Jan, 2017 - Comments: 0

Tools Cadence launched its Sigrity 2017 technology portfolio for PCB power and signal integrity signoff, adding a power topology viewer and editor, library management for power integrity models, and a PCI Express 4.0 compliance kit for checking signal integrity. Memory Spin Transfer Technologies delivered samples of fully functional ST-MRAM (spin transfer magneto-resistive random acces... » read more

Not All Software Is Like Elvis
By Frank Schirrmeister - 26 Jan, 2017 - Comments: 0

January is traditionally my look-back and outlook month. Five years ago my year-end wish had been a census of software developers, and it is fascinating how software in the context of verification has evolved since then (more on this below). Also, most years I go into my garage, dust off my collection of IEEE Spectrum print editions from January five, ten and 15 years back to assess which of th... » read more

2017: Tool And Methodology Shifts
By Brian Bailey - 26 Jan, 2017 - Comments: 0

As the markets for semiconductor products evolve, so do the tools that enable automation, optimization and verification. While tools rarely go away, they do bend like plants toward light. Today, it is no longer the mobile phone industry that is defining the direction, but automotive and the Internet of Things (IoT). Both of these markets have very different requirements and each creates their o... » read more

Hybrid Simulation Picks Up Steam
By Ann Mutschler - 26 Jan, 2017 - Comments: 0

As electronic products shift from hardware-centric to software-directed, design teams are relying increasingly on a simulation approach that includes multiple engines—and different ways to use those engines—to encompass as much of the system as possible. How engineers go about using these approaches, and even how they define them, varies greatly from one company to the next. Sometimes it... » read more

Power-Aware Analysis Solution
By Cadence - 25 Jan, 2017 - Comments: 0

By reviewing the classic (or traditional) SI methodology, analyzing high-speed design flow, and examining what is employed in Cadence Sigrity power and signal simulations using the SPEED2000, PowerSI, Transistor-to-Behavioral Model Conversion (T2BTM), and SystemSI tools, this paper explains how a general power-aware SI solution not only should be capable of performing SSN simulations, but also ... » read more

Blog Review: Jan. 25
By Jesse Allen - 25 Jan, 2017 - Comments: 0

Synopsys' Anand Thiruvengadam looks at why there's an increased need for mixed-signal verification. Mentor's Craig Armenti argues for incorporating design for reliability into PCB projects. Cadence's Paul McLellan reports from the latest in ESDA's Emerging Companies series about the roots and future of RISC-V. NI's James Kimery shares updates from the 3GPP Workshop on 5G in Vienna. ... » read more

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