tag: Cadence

Blog Review: Jan. 31
By Jesse Allen - 31 Jan, 2018 - Comments: 0

Cadence's Paul McLellan looks back at where TSMC was 30 years ago and the founding philosophy that made the foundry and fabless model work. In a video, Mentor's Colin Walls considers how to make the simplest possible multitasking scheduler with a one line RTOS. Synopsys' Sandeep Taneja checks out the technology behind airbags in cars and the role of the Motorola Serial Peripheral Interfac... » read more

Giant Auto Industry Disruption Ahead
By Ed Sperling - 29 Jan, 2018 - Comments: 5

The move to self-driving vehicles over the next decade or so will result in a massive restructuring of entire segments of the global economy that have evolved to create and support automobiles and the people who drive them. The shift will create many new jobs-particularly for semiconductors and electronic systems-and conservatively it will eliminate hundreds of thousands of existing ones. It... » read more

The Week In Review: Design
By Jesse Allen - 26 Jan, 2018 - Comments: 0

Security Addressing the Meltdown and Spectre speculative execution vulnerabilities has not gone smoothly. Intel's firmware update caused unexpected behavior and a higher than expected number of reboots for its Haswell and Broadwell chips, leading the company to recommend users stop patching until an updated version of the patch is available. Microsoft's attempts to fix the issue left some W... » read more

Verification Of Functional Safety
By Brian Bailey - 25 Jan, 2018 - Comments: 4

Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Functional safety for electrical and electronic systems is nothing new. It has been an important element of the military, aerospace and medical industries for many years. But the growing importance of functional safety within the automobile industry presents a number o... » read more

It Takes A Village… To Develop And Verify SoCs
By Frank Schirrmeister - 25 Jan, 2018 - Comments: 0

In my last blog post from 2017, “Design Chains Will Drive The Top 5 EDA Trends In 2018,” I had pointed to the importance of ecosystems for electronics development in general. From an EDA perspective, it also takes a village to shepherd the actual chip development with its complex verification and software development tasks. And the types of partnerships often depend on the application domai... » read more

7/5nm Timing Closure Intensifies
By Ann Mutschler - 25 Jan, 2018 - Comments: 1

Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Predictions: Methodologies And Tools
By Brian Bailey - 25 Jan, 2018 - Comments: 0

Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post. Intellectual property As designs get larger, it should be no surprise that the size of the [getkc id="43" kc_... » read more

Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm
By Cadence - 24 Jan, 2018 - Comments: 0

Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with r... » read more

Blog Review: Jan. 24
By Jesse Allen - 24 Jan, 2018 - Comments: 0

Mentor's Rich Edelman shares some tips for debugging complex UVM testbenches containing multiple agents, multiple checkers, and new HDL. Synopsys' Prasad Subudhi K. S. explains the PCIe PIPE 4.4.1 specification and the major improvements since 4.3, including better optimization in data flow and ultra-low power operations. Cadence's Paul McLellan steps back to before the Meltdown and Spect... » read more

Follow The Moving Money
By Ed Sperling - 18 Jan, 2018 - Comments: 1

Semiconductor economics are changing by market, by region, and by product node and packaging type, adding new complexity into decisions about which technology to use for which products and why. Money is the common denominator in all of these decisions, whether it's measured by return on invested capital, quarterly profits, or long-term investments that can include acquisitions, organic growt... » read more

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