tag: Cadence

Could Liquid IP Lead To Better Chips? (Part 3)
By Brian Bailey - 09 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Automotive Startup Activity Swelling
By Ann Mutschler - 04 Jan, 2018 - Comments: 0

According to AngelList, there are at least 6,600 automotive startups, with a $4.6 million average valuation. 475 of those are electric vehicle startups with a $5 million average valuation. Indeed, the electrification of vehicles and move towards autonomous driving is having a huge impact, the likes of which the automotive industry has never seen. This is causing the car manufacturers and Tie... » read more

Reshaping Automotive Design
By Ann Mutschler - 04 Jan, 2018 - Comments: 0

The entire automotive ecosystem is being reshaped by vehicle electrification, assisted and autonomous driving, and the connectivity needed to make it all work. So far, it's not clear just how smoothly this will all come together. In this redefined world, electronics and software will provide differentiation rather than mechanical engineering and possibly even brand name, creating change on a... » read more

Mixed-Signal Issues Worse At 10/7nm
By Ann Mutschler - 03 Jan, 2018 - Comments: 1

Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

Expanding Ecosystem Drives Auto Chip Gold Rush
By Thomas Wong - 03 Jan, 2018 - Comments: 0

Semiconductor chips designed to support automotive applications have been around for more than 40 years, which is a very long time in the technology business. These chips have been developed by semiconductor integrated device manufacturers (IDMs), which control every step of the design, manufacturing, test, qualification, reliability and quality aspects of these automotive chips. Special se... » read more

Reflection On 2017: Design And EDA
By Brian Bailey - 03 Jan, 2018 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Blog Review: Jan. 3
By Jesse Allen - 03 Jan, 2018 - Comments: 0

Ansys' Steve Pytel argues that increased signaling speeds and frequencies have led to signal integrity issues that circuit simulation alone cannot handle. Cadence's Paul McLellan dives into the details of Intel's 10nm process, including three layers of self-aligned quadruple patterning, contact-over-active-gate, and cobalt for contact fill. Mentor's Ron Press and Vidya Neerkundar argue th... » read more

Which Verification Engine?
By Ed Sperling - 02 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Reflections On 2017: Manufacturing And Markets
By Brian Bailey - 28 Dec, 2017 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts that looks at the pred... » read more

Is Verification Falling Behind?
By Brian Bailey - 21 Dec, 2017 - Comments: 1

Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy