Power Mode And State


By Luke Lang Low-power designs that use power shutoff (PSO) and multiple-supply voltage (MSV) will have circuits that operate at various voltages, including no voltage. To describe the combination of allowable voltages in a design, CPF uses power mode, and UPF 1.0 uses power state. In CPF, each power mode represents one combination of the states of all power domains. In UPF 1.0, each power ... » read more

Experts At The Table: Pain Points


By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Experts At The Table: Does 20nm Break System-Level Design?


By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

Emulation’s Winding Path To Success


By Ed Sperling Emulation was developed for verifying complex ICs when simulation was considered too slow. After more than a decade of very slow growth, however, sales have begun to ramp. There are several reasons for this shift. First, SoCs simply are becoming more complex, and the amount of verification that needs to be done to get a chip out the door can bring simulation to a crawl. Desig... » read more

Leveraging The Past


By Ann Steffora Mutschler It’s easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques, with 2.5D designs being a prime example. ... » read more

The Trouble With Models


By Ann Steffora Mutschler Models and modeling concepts seem to be on the tip of every tongue these days. Once the promise of sparking true ESL design, the use of system-level models has settled into something more like enabling software development. There is also talk of leveraging models across the supply chain, but is this really possible yet? The concept of doing this incremental refinem... » read more

PSL/SVA Assertions In SPICE


Assertion-based verification is a key aspect of any complete SoC or Silicon Realization flow. In this paper, we discuss how PSL (Property Specification Language)/SVA (System-V erilog Assertions) assertion semantics are extended for the first time to SPICE (Simulation Program with Integrated Circuit Emphasis)-level netlists and evaluated within a SPICE simulator, and present multiple examples an... » read more

Experts At The Table: IP Subsystems


By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that con... » read more

The Ins And Outs Of Directed Self-Assembly


By Mark LaPedus H.S. Phillip Wong, professor of electrical engineering at Stanford University and one of the leading experts on directed self-assembly (DSA) technology, sat down to discuss the future of this approach with Semiconductor Manufacturing & Design. With funding from the Semiconductor Research Corp. (SRC), Stanford is exploring contact-hole patterning and the design infrastructur... » read more

How Firm Is Firmware?


By Frank Schirrmeister When blogging recently about Xilinx’s presentation at the Cadence DAC 2012 EDA360 theater, which was given by Dave Beal, I ran across the diagram he had used to outline the “development stack” from hardware to software. Dave had described a virtual prototype to the audience as a functional model that recreates the WHAT rather than the HOW, duplicating the result ... » read more

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