tag: Cadence

Buying And Selling EDA Companies
By Ed Sperling - 24 Oct, 2013 - Comments: 0

EDA, arguably more than any other industry, has been built on the backs of engineering breakthroughs by startups. In aggregate, those startups are the backbone of tools that have made cell phones smart and which helped improved gas mileage on automobiles. Through an almost continuous stream of acquisitions, these startups have added to the top-line valuation of big EDA companies, and despite th... » read more

Trending Back To ASICs
By Ann Mutschler - 24 Oct, 2013 - Comments: 0

True to its cyclical nature, the semiconductor industry is swinging back toward ASICs from more diversified approaches such as FPGAs. This dynamic is evident at companies such as Apple. “At one point we thought Apple was being a contrarian,” said Drew Wingard, CTO at Sonics. “Everybody else on the systems side was shedding their silicon people. The easiest counterpoint to what Apple wa... » read more

Time To Rethink Verification
By Brian Bailey - 24 Oct, 2013 - Comments: 0

Verification traditionally has followed the path of the design team. When they change their methodology or tooling, verification engineers follow and attempts to incorporate it into their flow. The few times in the past when verification has attempted to lead, it has not ended well. An example of this was the attempt to get design teams using assertions. Assertions are proven to be valuable ... » read more

Verification 2.0: From Tool To Flow
By Frank Schirrmeister - 23 Oct, 2013 - Comments: 0

Recently, Cadence held a System-to-Silicon Verification Summit at which companies like Broadcom, Zenverge, NVIDIA, and Ambarella shared their experiences and visions for verification. In one of the keynotes, Brian Bailey shared his vision of how verification would transition from tools to flows. Brian’s presentation was quite insightful. He started with a brief status of where we are curre... » read more

Blog Review: Oct. 23
By Ed Sperling - 23 Oct, 2013 - Comments: 0

It was a good week for good questions. Cadence’s Brian Fuller asks what applications dream about—or rather what’s their potential. In the context of technology development, that’s worth pondering. Mentor’s Mike Jensen asks what will you be remembered for. There are a couple other important addendums to that, such as how long you will be remembered. And perhaps even more important, ... » read more

Approaching IP Quality From Many Angles
By Ann Mutschler - 17 Oct, 2013 - Comments: 0

As SoC design complexity has increased, semiconductor design IP and the industry around it has grown in its level of sophistication. This is great news for the users of that IP whose demands for quality, reliability and other deliverables have also been on the rise. Making sure users have what they need requires close collaboration between the semiconductor foundries, IP providers and of cou... » read more

The “Last Simple Node” And the Internet of Things
By Brian Fuller - 17 Oct, 2013 - Comments: 0

Power, performance and size are key targets that will enable the expected explosion of the Internet of Things (IoT). Today, most observers see the path to that running directly through 16/14nm finFET and below for the node’s ability to manage power and size and boost integration. Geoff Lees isn’t your average observer. The vice president and general manager of Freescale’s microcon... » read more

Tackling Verification Challenges With Interconnect Validation Tool
By Various Writers - 17 Oct, 2013 - Comments: 0

An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically, interconnect verification complexity also grows, considering the master/slave numbers, various protocols, different kinds of transactions, and multi-layered t... » read more

Blog Review: Oct. 16
By Ed Sperling - 16 Oct, 2013 - Comments: 0

Cadence’s Richard Goering follows Si2’s move into SPICE modeling following the acquisition of the Compact Model Council. Combining standards groups is a growing trend these days. Mentor’s Colin Walls points to the demise of reset buttons. You can always trip a circuit breaker, and usually turn off a device by pulling out the battery, but a reset button is simpler. Where did they go? ... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 11 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of IP portfolio marketing at TS... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy