tag: Cadence

The Week In Review: Oct. 11
By Mark LaPedus - 11 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling Demand is running high for DRAMs, thanks to last month’s fab fire at Hynix’ China plant. “The impact from Hynix' fab fire seems to be far more extensive than we had originally thought. We now think the factory is most likely up at the earliest by May/June 2014, which certainly provides robust pricing support for DRAM. Hynix is in the process of convertin... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Power Is A Global Issue
By Brian Bailey - 10 Oct, 2013 - Comments: 0

Power is now the No. 1 target in developing chips. In a keynote speech at the recent Cadence Verification Summit, James “Jim” Hogan—an EDA investor associated with companies such as Sonics, Nimbic, Solido, AutoESL, Altos and many others, and previously part of Cadence’s Telos venture arm—made the point that power is the big problem that needs to be solved. We all know that reducing... » read more

HDMI 2.0 Design And Verification Challenges
By Various Writers - 10 Oct, 2013 - Comments: 0

High-Definition Multimedia Interface (HDMI) is an audio/video (A/V) transmission protocol, which is omnipresent in consumer electronics, personal computing, and mobile products. Modern-day requirements of big screen resolutions, 3D, and multi-channel/multi-stream audio have pushed display devices to use a completely digital, high-speed transmission media, requiring a multi-layered protocol like... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 10 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate marketing at Atrenta; ... » read more

Flexibility Improves Memory Interface Bandwidth
By Ann Mutschler - 10 Oct, 2013 - Comments: 0

In today’s SoCs, memory is the heart or at least one of the main elements of the design. As such, designing them carefully is paramount to achieving the best bandwidth, performance and power. Performance is very important to be able to access the memory and to trade and store information from different IPs with shared memories or local memories. From the power perspective, every access to... » read more

Blog Review: Oct. 9
By Ed Sperling - 09 Oct, 2013 - Comments: 0

By Ed Sperling Mentor’s Simon Favre raises an interesting question: Why are 450mm wafers and EUV lithography related? The answer may surprise you. In his second broadcast, Cadence’s Brian Fuller interviews Gary Smith about where EDA will grow, why industry consolidation is a myth and why there is a dearth of reliable information about the electronics industry. Synopsys’ Mick Posner... » read more

Can the EDA Software Industry Evolve Successfully?
By Brian Fuller - 09 Oct, 2013 - Comments: 0

The most fundamental industry question of the moment is uncomfortably simple: Can EDA move beyond itself? Industry growth is sluggish, and innovation via startups seems—seems because that’s a flabby statement—static today. Cadence CEO and venture capitalist Lip-bu Tan put it plainly in an interview: “If you look at the bigger picture, the semiconductor industry has not grown for ... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 04 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 04 Oct, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of ... » read more

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