tag: Cadence

Blog Review: Oct. 3
By Ed Sperling - 03 Oct, 2013 - Comments: 0

Cadence’s Brian Fuller rolls out a twice-monthly TV program called “Unhinged,” which he bills as a cross between The Daily Show, Letterman and ESPN. The intro is a classic. Who needs coffee? Synopsys’ Karen Bartleson interviews Bob Metcalfe, co-inventor of Ethernet, creator of Metcalfe’s Law—which has withstood the test of time quite well—on why Ethernet still really important.... » read more

Why does EUV matter?
By Brian Bailey - 01 Oct, 2013 - Comments: 0

By Brian Bailey The end of Moore’s Law has been predicted for almost as long as the law has existed. It normally comes down to some great technological barrier that cannot be breached, only to find that a solution is just around the corner and the concerns fade until the next barrier is identified. At DAC this year (2013), there were many predictions about why Moore’s Law will end in th... » read more

Productivity, Predictability And Use-Model Versatility
By Various Writers - 26 Sep, 2013 - Comments: 0

Hardware-assisted verification and prototyping has become a mandatory requirement to allow design teams to gain confidence that a chip tape out can be initiated. The choice of the right hardware-accelerated engine is driven by its productivity, predictability, and use-model versatility, all impacting the key concern of users how to remove bugs. The XP Platform allows design teams to get to the ... » read more

Buying And Selling EDA Companies
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Buying companies is the easy part. Integrating them is the hard part. It’s also the point where most acquisitions that go awry actually run into problems. There are widely different strategies for how to accomplish integration. Sometimes they work, other times they don’t. And sometimes both companies are surprised by the outcome—for better or worse. “Either you thi... » read more

Experts At The Table: How To Improve IP Quality
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of I... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

How Much Verification Can One Engineer Handle?
By Frank Schirrmeister - 25 Sep, 2013 - Comments: 0

By Frank Schirrmeister When reviewing the agenda of our upcoming Verification Summit here in San Jose this Thursday, the question came to mind of who can actually execute the required complex verification tasks. Can they understand enough detail in hardware, software, and the system aspects to efficiently rid the design of bugs? The reality is that the task requires not one engineer who can do... » read more

The Week In Review: Sept. 23
By Mark LaPedus - 23 Sep, 2013 - Comments: 0

By Mark LaPedus For some time, Apple’s iPhones have incorporated a separate RF switch and diversity switch from Peregrine Semiconductor (PSMI). The switches are based on a silicon-on-insulator (SOI) variant called silicon-on-sapphire (SOS). Murata takes Peregrine’s RF switches and integrates them into a module. Doug Freedman, an analyst with RBC Capital, said Apple is no longer using PSMI�... » read more

The Week In Review: Sept. 20
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

Mask Data Prep Issues Compounding At 20nm
By Ann Mutschler - 19 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

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