tag: Cadence

Should EDA Heads Be In The Cloud?
By Brian Fuller - 19 Sep, 2013 - Comments: 0

Consider the following two comments about cloud computing and electronic design automation: “Over time everybody will move to the cloud in EDA at least in some extent.”—Raik Brinkmann, CEO of OneSpin Solutions. “We put a substantial effort into that, and of all the things we've done in the last 25 years this is probably the single one where the result is essentially zero. I don't ... » read more

Blog Review: Sept. 18
By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

The Week In Review: Sept. 16
By Mark LaPedus - 16 Sep, 2013 - Comments: 0

By Mark LaPedus In June, Crucial.com teamed up with Lou Ferrigno to invite all frustrated computer users to submit a short video showing their most fearsome, frustration-filled and computer-induced roar. Each video was evaluated according to a variety of factors, including volume, enthusiasm, perceived distress, frustration, anxiety, irritation and overall hopelessness. The memory module suppl... » read more

The Week In Review: Sept. 13
By Ed Sperling - 13 Sep, 2013 - Comments: 0

By Ed Sperling Cadence unveiled its next-generation emulation platform, greatly boosting the speed by up to 60x for embedded OS verification and by up to 10x for hardware/software verification. Overall, Cadence says the platform doubles verification productivity with a capacity of up to 2.3 billion gates. Cadence also reported that its mixed-signal LP flow allowed Silicon Labs to cut its MCU p... » read more

Five Emerging DRAM Interfaces You Should Know For Your Next Design
By Various Writers - 12 Sep, 2013 - Comments: 0

Producing DRAM chips in commodity volumes and prices to meet the demands of the mobile market is no easy feat, and demands for increased bandwidth, low power consumption, and small footprint don’t help. This paper reviews and compares five next-generation DRAM technologies— LPDDR3, LPDDR4, Wide I/O 2, HBM, and HMC—that address these challenges. To view this white paper, click here. » read more

New Risk Factors For SoCs
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Third-party IP is becoming increasingly important in SoC designs. It saves development time and adds unique value. It also can improve performance and lower power, because a company specializing in IP frequently can build and optimize it better than a company that builds entire chips. But there are also plenty of landmines in IP integration, and there is a growing concern abo... » read more

Experts At The Table: Who Takes Responsibility?
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate market... » read more

Power Grid Analysis Heats Up At 20nm
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

Blog Review: Sept. 11
By Ed Sperling - 11 Sep, 2013 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang has unearthed the weirdest USB video ever produced—a dancing USB lighter. The messaging is pretty bizarre, too. Cadence’s Brian Fuller takes a whirlwind tour of the engineering accomplishments for the week. Check out the T-shirt message. Clearly they’re not talking about semiconductor engineers. Mentor’s Colin Walls looks at the Lua scripting... » read more

The Week In Review: Sept. 9
By Mark LaPedus - 09 Sep, 2013 - Comments: 0

By Mark LaPedus SK Hynix’ DRAM fab in China caught on fire. The fire caused one minor injury, but it did not impact the equipment, according to reports. SK Hynix will re-open the fab soon, according to reports. Bob Halliday, Applied Materials’ CFO, gave a presentation at an analyst event, saying: “I think there’s probably more technology inflections going on right now than in years.... » read more

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