tag: capacitance

Boosting Analog Reliability
By Ed Sperling - 17 Jan, 2019 - Comments: 0

Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

A Method to Measure Die Pad Capacitance
By Cadence - 24 Oct, 2018 - Comments: 0

This paper defines a method to measure the chip die pad capacitance using time delay reflectometry (TDR). This method is useful for measuring the low-value capacitance that is present at the end of a transmission line. In all protocol specifications, pad capacitance is an important electrical parameter to be measured because it directly affects the bandwidth. However, it is a challenge to me... » read more

Electromagnetic Crosstalk Considerations In Low Power Designs
By Magdy Abadir - 19 May, 2018 - Comments: 0

By Magdy Abadir, Padelis Papadopoulos, and Yehea Ismail
 Power consumption continues to be a critical design metric in high-performance mobile electronics. In order to meet the aggressive power budget targets, chips today need to operate at extremely low power levels, which increases the critical signals’ susceptibility to electromagnetic (EM) crosstalk effects. Because a low-power So... » read more

IP Electromagnetic Crosstalk Requires Contextual Signoff
By Magdy Abadir - 16 Apr, 2018 - Comments: 0

By Magdy Abadir and Anand Raman Continuous advancement in technology scaling is enabling the emergence of high-performance application markets such as artificial intelligence, autonomous cars and 5G communication. These electronic systems operate at multi-GHz speed, while consuming the lowest amount of power possible leaving very little margin for error. Chips in these systems are highly in... » read more

Why Inductance Is Good for Area, Power and Performance
By Magdy Abadir - 12 Mar, 2018 - Comments: 0

By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Tech Talk: 5/3nm Parasitics
By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

Pushing Performance Limits
By Brian Bailey - 08 Feb, 2018 - Comments: 0

Trying to squeeze the last bit of performance out of a chip sounds like a good idea, but it increases risk and cost, extends development time, reduced yield, and it may even limit the environments in which the chip can operate. And yet, given the amount of margin added at every step of the development process, it seems obvious that plenty of improvements could be made. "Every design can be o... » read more

Managing Parasitics For Transistor Performance
By Katherine Derbyshire - 30 Jan, 2017 - Comments: 3

The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry's history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discoun... » read more

BEOL Issues At 10nm And 7nm (part 2)
By Ed Sperling - 04 Jan, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

7nm Power Issues And Solutions
By Preeti Gupta - 16 Nov, 2016 - Comments: 0

Being able to achieve 35% speed improvement, 65% power reduction and 3.3X higher density makes adopting a 7nm process for your next system-on-chip (SoC) design seem like an easy decision. However, with $271 million in estimated total design cost and 500 man-years it would take to bring a mid-range 7nm SoC to production, companies need to carefully weigh the benefits against the cost of designin... » read more

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