tag: Coventor

Blog Review: Nov. 3
By Jesse Allen - 03 Nov, 2021 - Comments: 0

In a blog for Arm, Matthew Griffin of the 311 Institute warns that cybersecurity is an increasingly pressing problem, with large criminal organizations raking in large sums of money and attacks able to impact a wide range of physical systems. Cadence's Paul McLellan checks out Google's video encoder chip and how it helps lower the CPU recycles required by the vast number of videos uploaded t... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Performance
By Yu De Chen - 21 Oct, 2021 - Comments: 0

Profile variation is one of the most important problems during semiconductor device manufacturing and scaling. These variations can degrade both chip yield and device performance.  Virtual fabrication can be used to study profile variation in a very effective and economical manner and avoid process cycle time and wafer cost in the fab. In this short article, we will review the impact of STI (s... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 01 Oct, 2021 - Comments: 0

Market research For some time, the semiconductor industry has experienced acute shortages. The automotive industry has suffered the most. When will this all end? “Shortages have become more acute for many products in the near term because the growth in demand is greater than the increase in wafer and packaging capacity that was anticipated by the foundry and semiconductor vendors. To date... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Device Performance
By Coventor - 15 Sep, 2021 - Comments: 1

In this paper, a 5nm FinFET flow was built using the SEMulator3D virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated usi... » read more

Blog Review: Sept. 15
By Jesse Allen - 15 Sep, 2021 - Comments: 0

Synopsys' Ian Land and Ricardo Borges examine how radiation modeling can help ensure semiconductor components will survive while housed in equipment that is orbiting our planet or traveling through deep space over extensive periods of time. Siemens EDA's Rich Edelman explores why writing coverage is an art requiring imagination, practice, and patience, along with some tips on how to improve.... » read more

Blog Review: Sept. 1
By Jesse Allen - 01 Sep, 2021 - Comments: 0

Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava continue their exploration of MRAM simulation by explaining stochasticity experiments and a characterization framework that focuses on the MRAM behavior statistical analysis. Siemens EDA's Neil Johnson shows how performance profiling can be used to identify testbench code that could slow down simulation and when to start using i... » read more

Blog Review: Aug. 25
By Jesse Allen - 25 Aug, 2021 - Comments: 0

Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava introduce an open source framework and compact model for the simulation, characterization, and analysis of MRAM magnetic tunnel junctions. Siemens EDA's Chris Spear continues the tutorial on SystemVerilog class variables with a look at how to use the $cast() system task to copy between base and derived class variables. Syno... » read more

Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions
By Michael Hargrove - 19 Aug, 2021 - Comments: 0

It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

Process Variation Analysis Of Device Performance Using Virtual Fabrication — Methodology Demonstrated On A CMOS 14-nm FinFET Vehicle
By Coventor - 18 Aug, 2021 - Comments: 0

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

Blog Review: Aug. 11
By Jesse Allen - 11 Aug, 2021 - Comments: 0

Arm's Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay. Cadence's Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it. A Synopsys writer explains the new LP... » read more

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