tag: Coventor

Blog Review: Aug. 25
By Jesse Allen - 25 Aug, 2021 - Comments: 0

Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava introduce an open source framework and compact model for the simulation, characterization, and analysis of MRAM magnetic tunnel junctions. Siemens EDA's Chris Spear continues the tutorial on SystemVerilog class variables with a look at how to use the $cast() system task to copy between base and derived class variables. Syno... » read more

Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions
By Michael Hargrove - 19 Aug, 2021 - Comments: 0

It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

Process Variation Analysis Of Device Performance Using Virtual Fabrication — Methodology Demonstrated On A CMOS 14-nm FinFET Vehicle
By Coventor - 18 Aug, 2021 - Comments: 0

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

Blog Review: Aug. 11
By Jesse Allen - 11 Aug, 2021 - Comments: 0

Arm's Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay. Cadence's Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it. A Synopsys writer explains the new LP... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 06 Aug, 2021 - Comments: 0

Chipmakers Taiwan’s Foxconn continues to expand its efforts in the semiconductor business. Foxconn has acquired a 6-inch wafer fab and the equipment from Taiwan’s Macronix for NT$2.52 billion (US$90.76 million). With the fab, Foxconn plans to enter the wideband gap semiconductor market, namely silicon carbide (SiC). SiC devices are used in electric vehicles, a market that Foxconn is making... » read more

Using A Virtual DOE To Predict Process Windows And Device Performance Of Advanced FinFET Technology
By Qingpeng Wang - 03 Aug, 2021 - Comments: 0

By Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang, and Joseph Ervin Introduction With continuing finFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch rate on a wafer is dependent upon existing feature sizes and local pattern density. Uninten... » read more

MEMS: New Materials, Markets And Packaging
By Ed Sperling - 28 Jul, 2021 - Comments: 1

Semiconductor Engineering sat down to talk about future developments and challenges for microelectromechanical systems (MEMS) with Gerold Schropfer, director of MEMS products and European operations in Lam Research's Computational Products group, and Michelle Bourke, senior director of strategic marketing for Lam's Customer Support Business Group. What follows are excerpts of that conversation.... » read more

Blog Review: July 28
By Jesse Allen - 28 Jul, 2021 - Comments: 0

Synopsys' Chris Clark considers potential vulnerabilities in automotive over-the-air updates and best practices and new standards the industry can implement to improve security of vehicle software updates. Cadence's Paul McLellan gets a look at expected new fab construction in the coming years and where capacity is being focused. Siemens' Robin Bornoff dives into electromagnetic simulatio... » read more

The Effects Of Poly Corner Etch Residue On Advanced FinFET Device Performance
By Coventor - 21 Jul, 2021 - Comments: 0

In this paper, we study the effect of poly corner residue during a 5nm FinFET poly etch process using virtual fabrication. A systemic investigation was performed to understand the impact of poly corner residue on hard failure modes and device performance. Our results indicate that larger width and height residues can lead to a hard failure by creating a short between the source/drain epitaxy an... » read more

Blog Review: June 30
By Jesse Allen - 30 Jun, 2021 - Comments: 0

Siemens EDA's Chris Spear considers what classes should represent in SystemVerilog and offers two major categories along with some helpful UVM tips. Cadence's Paul McLellan listens in on keynotes at the recent TSMC Technology Symposium, including TSMC CEO C. C. Wei's introduction some of the fab's new offerings, such as an automotive-focused N5 process. Synopsys' Dennis Kengo Oka notes th... » read more

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