tag: Coventor

Blog Review: Sept. 28
By Jesse Allen - 28 Sep, 2022 - Comments: 0

Cadence's Paul McLellan shares more highlights from the recent Hot Chips, including some very large chips and accelerators for AI and deep learning, new networks and switches, and mobile and edge processors. Synopsys' Marc Serughetti considers the different use cases for digital twins in automotive and how they can help determine the impact of software on verification, test, and validation a... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

A Study Of The Impact Of Line Edge Roughness On Metal Line Resistance Using Virtual Fabrication
By Coventor - 15 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line-to-line spacing, which introduces higher metal line resistance and line-to-line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitch... » read more

Blog Review: Aug. 24
By Jesse Allen - 24 Aug, 2022 - Comments: 0

Synopsys' Manuel Mota presents an overview of some of the newest multi-chip module packaging types and their advantages and disadvantages for different kinds of applications, as well as the importance of die-to-die interfaces. Cadence's Steve Brown finds that innovative products require that electronics be analyzed in the context of the environment in which they run, making mechanical and el... » read more

Big Changes In Architectures, Transistors, Materials
By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

3D NAND Virtual Process Troubleshooting And Investigation
By Brett Lowe - 18 Aug, 2022 - Comments: 0

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form of unanticipated negative interactions between upstream and downstream process modules. These barriers can create a long delay in the development cycle and increase costs. ... » read more

Blog Review: Aug. 3
By Jesse Allen - 03 Aug, 2022 - Comments: 0

Siemens' Patrick Hope explains the growing importance of choosing the right laminate for PCB designs and how to read a material datasheet to compare important electrical, thermal, and mechanical properties. Synopsys' Yankin Tanurhan argues that as the number of sensors being integrated in automotive systems increases to enable new ADAS and autonomy capabilities, building security and quality... » read more

Scaling, Advanced Packaging, Or Both
By Ed Sperling - 01 Aug, 2022 - Comments: 0

Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

Quantum Computers And CMOS Semiconductors: A Review And Future Predictions
By Michael Hargrove - 16 Jun, 2022 - Comments: 0

With the advent of quantum computing, the need for peripheral fault-tolerant logic control circuitry has reached new heights. In classical computation, the unit of information is a “1” or “0”. In quantum computers, the unit of information is a qubit which can be characterized as a “0”, “1”, or a superposition of both values (known as a “superimposed state”). The control c... » read more

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