tag: ESD

A Reliability Baseline Is Essential For Today’s Complex IC Designs
By Matthew Hogan - 22 Feb, 2018 - Comments: 0

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Chip Aging Accelerates
By Ed Sperling - 14 Feb, 2018 - Comments: 1

Reliability is becoming an increasingly important proof point for new chips as they are rolled out in new markets such as automotive, cloud computing and industrial IoT, but actually proving that a chip will function as expected over time is becoming much more difficult. In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed ... » read more

How Robust Is Your ESD Protection? Are You Sure?
By Derong Yan - 08 Feb, 2018 - Comments: 0

Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increa... » read more

Improving Automotive Reliability
By Annapoorna Krishnaswamy - 16 Oct, 2017 - Comments: 0

Semiconductor reliability requirements are rapidly evolving. New applications such as ADAS/self-driving cars and drones are pushing the limits for system reliability. A mobile phone that overheats in your pocket is annoying. In automobiles, it's a much different story. Overheating can impact the operation of backup sensors, which alert the driver that a pedestrian or obstacle is behind them.... » read more

Addressing Thermal Reliability In Next-Gen FinFET Designs
By Anusha Prakash - 18 Sep, 2017 - Comments: 0

The next generation of chips on the 10/7nm finFET processes will be able to cram more devices into same area while also boosting performance, but there's a price to pay for that. The 3D fin structures trap heat, so the the temperature rises on the device and there is no way to dissipate that heat. This combination of higher current density, higher performance and higher temperature has a det... » read more

How Reliable Are FinFETs?
By Ann Mutschler - 16 Aug, 2017 - Comments: 1

Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

Transient Power Problems Rising
By Ann Mutschler - 08 Jun, 2017 - Comments: 0

Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

Assessing ESD Sensitivity Of Interface IP Using Charged Device Model
By Synopsys - 07 Dec, 2016 - Comments: 0

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, especially from the completion of the silicon wafer processing to when the device is assembled in the system. The most commonly used ESD test models are the Human Body Model (HBM) and the Charged Device Model (CDM). Both models assess the ESD sensitivity of a device, however due to the rapi... » read more

Partitioning For Power
By Ed Sperling - 14 Nov, 2016 - Comments: 0

Examine any smartphone design today and most of the electronic circuitry is "off" most of the time. And regardless of how many processor cores are available, it's rare to use more than a couple of those cores at any point in time. The emphasis is shifting, though, as the mobility market flattens and other markets such as driver-assisted vehicles and IoT begin gaining traction. In a car, turn... » read more

Implementing ESD Protection In Today’s SoCs
By Karthik Srinivasan - 08 Sep, 2016 - Comments: 0

As the semiconductor industry transitions to FinFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts. Technology ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy