tag: EUV

Will 7nm And 5nm Really Happen?
By Mark LaPedus - 14 Jul, 2014 - Comments: 2

Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

Stacked Die Are Coming Soon. Really
By Ed Sperling - 10 Jul, 2014 - Comments: 3

Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner. But something very fundament... » read more

How Much Multipatterning?
By Ed Sperling - 19 Jun, 2014 - Comments: 2

The latest consensus among litho experts is that extreme ultraviolet (EUV) will appear in the market sometime in coming months in a commercially viable form. The only question is the degree of commercially viability, and what it will actually cost. While some debate lingers about whether EUV will ever get going, the general feeling is that enough progress has been made recently to make it work.... » read more

Has The IC Industry Hit A ‘Red Brick Wall’?
By Mark LaPedus - 19 Jun, 2014 - Comments: 2

In the mid-1980s, the semiconductor industry was in a crisis. Chipmakers were looking for ways to break the magical one-micron barrier. Many thought X-ray lithography would be required to break the barrier, but as it turned out, traditional optical technology did the trick. And the industry marched on. Then, in 2000 or so, the IC industry was nearing the so-called “red brick wall,” which... » read more

EDA Races To 7nm, Despite Litho Uncertainties
By Ann Mutschler - 16 May, 2014 - Comments: 0

It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

The Bumpy Road To FinFETs
By Mark LaPedus - 15 May, 2014 - Comments: 2

The shift from planar transistors to finFETs is a major inflection point in the IC industry. FinFETs are expected to enable higher performance chips at lower voltages. And the next-generation transistor technology also could allow the industry to extend CMOS to the 10nm node and perhaps beyond. But as it turns out, finFET technology is also harder to master than previously thought. For exam... » read more

FinFET Learning
By Ed Sperling - 08 May, 2014 - Comments: 0

FinFETs are not simple to work with. They’re difficult to manufacture, tricky to design, and they run the risk of greatly increased dynamic power density—particularly at 14/16nm, where extra margin is hard to justify—which affects everything from electromigration to signal integrity. Moreover, while finFETs have been on the drawing board for more than a decade, it’s taken four years ... » read more

Follow The Investments
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Where is design heading over the next few years. The best way to tell that is to find out where the development dollars are going, and foundries and tools always precede actual designs. The foundries are starting to spend money—lots of it—on finFETs and 28nm. And while they’re talking about 2.5D and 3D, the money isn’t going there just yet. In fact, there are two different processes ... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

What If EUV Fails?
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme. Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now,... » read more

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