tag: finFETs

Uncertainty Ahead
By Ed Sperling - 11 Apr, 2013 - Comments: 0

If finFETs work as planned, it’s likely they will show up in every complex SoC for decades to come. Adding another dimension to transistors has enormous potential at advanced nodes, and maybe even at older nodes. 3D transistors also could be part of stacked die, and they can be combined with fully depleted SOI—two other options for reducing power. Moreover, it’s likely that whatever G... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 11 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts ... » read more

The Next Limiting Factor
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

It’s an interesting time in the semiconductor industry. Nodes continue to shrink, we’re on the verge of adopting a new type of transistor (finFET), and there’s also a shift away from planar CMOS – to name a few things on the horizon. What’s also extremely interesting is how design automation and semiconductor manufacturing technology continues to keep the pace with it all. However,... » read more

Throw In The Kitchen Sink
By Ed Sperling - 05 Apr, 2013 - Comments: 0

By Ed Sperling The number of options available for reducing power and improving performance are increasing for the first time in a decade. This is good news for chipmakers. It’s far less clear who stands to benefit on the tools, IP, capital equipment and manufacturing side. Choice is always a good thing in design. It allows teams to trade off one IP block for another, based upon the needs... » read more

Physical Verification Of FinFETs And Fully Depleted SOI
By Various Writers - 28 Mar, 2013 - Comments: 0

It has become very difficult to effectively shrink traditional bulk planar transistors below 20nm due to physical effects that become dominant in very short conduction channels. The major impediment is an unacceptable rise in power consumption due to significant leakage currents. New transistor architectures are being adopted that offer a solution for these short-channel effects and allow trans... » read more

Wanted: New Metrology Funding Models
By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing. Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology. ... » read more

What’s In A Name?
By Subi Kengeri - 20 Mar, 2013 - Comments: 0

By Subi Kengeri Consumers continue to demand smaller, faster and more energy-efficient electronic devices, driving the semiconductor industry to accelerate development of commercially viable chips on more advanced nodes. However, these new nodes don’t just appear by magic. It takes a great deal of careful planning to develop and deliver a process technology platform that offers competitivene... » read more

LP Verification
By Ed Sperling - 08 Mar, 2013 - Comments: 0

Functional verification has been a consideration throughout the design flow for the past several process nodes. Low power verification has been more of an afterthought. That’s beginning to change, though, as the challenge of integrating IP blocks and the physical effects of shrinking wires and RC delays in interconnects begin affecting power and performance in designs. What’s becoming cl... » read more

Designing with FinFETs: The Opportunities and the Challenges
By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

Getting Ready For High-Mobility FinFETs
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node. Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts t... » read more

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