tag: floorplanning

The Ultimate Shift Left
By Brian Bailey - 09 Mar, 2017 - Comments: 0

Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

How High-Level Synthesis Was Used to Develop An Image-Processing IP Design From C++ Source Code
By Cadence - 07 Dec, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Power Confounds, Challenges
By Ann Mutschler - 14 Jul, 2016 - Comments: 0

I have to admit I’m always surprised to hear that design teams are not using tools to the fullest extent possible, leaving valuable power saving opportunities on the table, until I remember how daunting it is to get it all right without tremendous experience, expertise, and the right tools. I’m also always fascinated to learn about less-obvious effects from power. To this point, Aveek... » read more

Next-Generation RTL Floorplanning
By Mentor, a Siemens Business - 10 Feb, 2016 - Comments: 0

Mentor’s physical RTL synthesis tools, including RealTime Designer and next-generation products, have the unique technology to pull placement ahead of synthesis and address the need for RTL floorplanning. Mentor’s physical RTL synthesis tools offer higher capacity, faster runtimes, optimal QoR, and physical awareness during RTL synthesis by optimizing at a higher level of abstraction and u... » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning
By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

Tear Down The Wall Between Front-End And Back-End Teams
By Kurt Shuler - 25 Jun, 2015 - Comments: 1

As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

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