tag: line-edge roughness

Strategies For Faster Yield Ramps On 5nm Chips
By Laura Peters - 12 Apr, 2022 - Comments: 0

Leading chipmakers TSMC and Samsung are producing 5nm devices in high volume production and TSMC is forging ahead with plans for first 3nm silicon by year end. But to meet such aggressive targets, engineers must identify defects and ramp yield faster than before. Getting a handle on EUV stochastic defects — non-repeating patterning defects such as microbridges, broken lines, or missing con... » read more

Finding, Predicting EUV Stochastic Defects
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography. Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the perf... » read more

Inspecting, Patterning EUV Masks
By Mark LaPedus - 06 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Effects Of A Random Process Variation On The Transfer Characteristics Of A Fundamental Photonic Integrated Circuit Component
By Coventor - 18 Sep, 2019 - Comments: 0

Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

Target: 50% Reduction In Memory Power
By Brian Bailey - 11 Apr, 2019 - Comments: 3

Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 22 Mar, 2019 - Comments: 0

Chipmakers TrendForce released its foundry rankings for the first quarter of 2019. TSMC is still the clear leader, followed in order by Samsung, GlobalFoundries and UMC, according to the firm. It was a tough quarter for all foundries. Samsung has rolled out its new High Bandwidth Memory (HBM2E) product. The new solution, called Flashbolt, is the industry’s first HBM2E to deliver a 3.2Gbps... » read more

EUV Arrives, But More Issues Ahead
By Katherine Derbyshire - 21 Mar, 2019 - Comments: 5

EUV has arrived. After decades of development and billions of dollars of investment, EUV lithography is taking center stage at the world’s leading fabs. More than 20 years after ASML's extreme ultraviolet lithography research program began, and nearly a decade after its first pre-production exposure tools, the company expects to deliver 30 EUV exposure systems in 2019. That is nearly doubl... » read more

Using Sensor Data To Improve Yield And Uptime
By Ed Sperling - 21 Feb, 2019 - Comments: 2

Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures. Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how,... » read more

Variation Issues Grow Wider And Deeper
By Ed Sperling - 24 Jan, 2019 - Comments: 0

Variation is becoming more problematic as chips become increasingly heterogeneous and as they are used in new applications and different locations, sparking concerns about how to solve these issues and what the full impact will be. In the past, variation in semiconductors was considered a foundry issue, typically at the most advanced process node, and largely ignored by most companies. New p... » read more

Analyzing Worst-Case Silicon Photonic Device Performance Through Process Modeling And Optical Simulation
By Ryan Miller - 24 Jan, 2019 - Comments: 0

Silicon photonics is an emerging and rapidly-expanding design platform that promises to enable higher-bandwidth communication and other applications. One of the best qualities of silicon photonics is its ability to leverage existing CMOS fabrication equipment and process flows. However, this means that it is subject to the same process defects and variations. Previous blog posts [References 1,2... » read more

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