Challenges Mount For Patterning And Masks

By Mark LaPedus - 30 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Uday Mitra, vice president and chief technology officer for the Etch Business Unit at [getentity id="22817" e_name="Applied Materials"]; Pawitter Mangat, senior manager and deputy director for EUV lithography at [getentity id="22819" comment="GlobalFoundries"]; Aki Fujimura, chief executive at [getentity id="228... » read more

Challenges Mount For Patterning And Masks

By Mark LaPedus - 19 Mar, 2015 - Comments: 0

Tech Talk: Inverse Lithography

By Ed Sperling - 11 Dec, 2014 - Comments: 0

D2S’ Leo Pang talks with Semiconductor Engineering about lithography, inverse lithography, photomasks, where the problems are, and what needs to be done to move forward. [youtube vid=mn8JWaP8Z68] » read more

Self-Aligned Double Patterning, Part One

By David Abercrombie - 15 May, 2014 - Comments: 0

I’m sure most of you have seen a Rorschach test ink blot (Figure 1). Psychiatrists ask the subjects to tell them what they “see” in the ink blot. The answers are used to characterize the respondent’s personality and emotional functioning. I am never sure if I would feel more uncertain being the psychiatrist asking the question, or the subject trying to decide what to say, given there ar... » read more

One-On-One: Linyong Pang

By Mark LaPedus - 12 May, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss trends in the lithography and photomask business with Linyong “Leo” Pang, the new chief product officer and executive vice president at D2S, which focuses on model-based mask data preparation as well as other mask writing technologies. What follows are excerpts of that conversation. SE: Before you arrived at D2S you were at Luminescent, whic... » read more

Mask Issues Ahead

By eBeam Initiative - 17 Apr, 2014 - Comments: 0

It's not just the lithography that's getting complicated. Check out this video by Dai Nippon Printing's Naoya Hayashi. [youtube vid=a6WmvhTdEv4] » read more

Interconnect Challenges Grow

By Mark LaPedus - 20 Feb, 2014 - Comments: 0

Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

Mask Data Prep Issues Compounding At 20nm

By Ann Mutschler - 19 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to mask data prep—the step in the design and manufacturing flow that occurs just after optical proximity correction (OPC)—challenges have continued to rise with the subsequent moves to smaller geometries. This is driven by the scaling demands of delivering about a 50% area shrink from node to node on a two-year cycle, and thus dictates the lithog... » read more

A Mischievous Muse

By Marc David Levenson - 20 Sep, 2012 - Comments: 0

By Marc David Levenson Moorissa, the muse of high technology, enjoys playing practical jokes on the mask-makers, whose annual meeting was the week of Sept. 10 in Monterey. It started long ago…For example, no sooner had mask makers learned how to write precise 1X masks with fancy electron beams than the wafer printing industry went to reduction steppers, negating the advantages of all that pr... » read more

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tag: masks

Challenges Mount For Patterning And Masks

Challenges Mount For Patterning And Masks

Tech Talk: Inverse Lithography

Self-Aligned Double Patterning, Part One

One-On-One: Linyong Pang

Mask Issues Ahead

Interconnect Challenges Grow

Mask Data Prep Issues Compounding At 20nm

A Mischievous Muse