tag: Mentor Graphics

You Can’t Get There From Here
By David Abercrombie - 17 Jul, 2013 - Comments: 0

By David Abercrombie In my last article, I reviewed the aspects of cell design that are affected by double patterning (DP). This time, I’ll discuss how automatic routing is affected by DP. Let’s begin by looking at the interaction between decisions made at the cell design level and decisions made at the routing level. One key routing decision is whether or not you will allow cell-to-cel... » read more

Automation of Sample Plan Creation For Process Model Calibration
By Various Writers - 17 Jul, 2013 - Comments: 0

The process of preparing a sample plan for optical and resist model calibration has always been tedious. Not only because it is required to accurately represent full chip designs with countless combinations of widths, spaces and environments, but also because of the constraints imposed by metrology which may result in limiting the number of structures to be measured. Also, there are other limit... » read more

The Week In Review: July 15
By Mark LaPedus - 15 Jul, 2013 - Comments: 0

By Mark LaPedus There are more problems surfacing with extreme ultraviolet (EUV) lithography. Yes, the light source remains a problem, but the resists appear to be in decent shape. “The next challenge is the mask blank,” said Stefan Wurm, director of Sematech’s lithography program. The new problem involves ion beam deposition, which apparently is causing defects and overfill on EUV masks... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 15 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: Does the increasing collaboration in the ecos... » read more

The Week In Review: July 12
By Ed Sperling - 12 Jul, 2013 - Comments: 0

By Ed Sperling Cadence rolled a new version of its layout suite of tools for electrically aware designs, allowing design teams to check on electrical issues while the layout is being done. The company says this can reduce circuit design time by up to 30%, in addition to optimizing for performance and area. Cadence also announced a deal with Global Unichip, which successfully taped out a 20nm ... » read more

Software Debug Gets Tricky
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler As designs continue to grow in size and complexity, that complexity has led to an increasing number of processing cores. Additional cores, in turn, allow for additional software to be run on those cores, and debugging the software becomes critical. Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to d... » read more

The Controversial Spec
By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler Design sophistication and complexity has made it increasingly difficult to fully specify the expected behavior of a block in an SoC, but this is necessary for design and verification teams. How do you write a “good” and “complete” specification of functionality? It turns out that the discussion of defining what a good and complete specification is and how t... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 11 Jul, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

Electromigration Analysis At Advanced Nodes
By Valeriy Sukharev - 11 Jul, 2013 - Comments: 0

Introduction Continuous downward scaling is challenging electromigration (EM) signoff using traditional EM checking approaches. The size reduction of metal line cross sections results in higher current densities, which are governed by technology scaling. With the transition to advanced technological nodes, the widely-predicted decrease in EM lifetime is responsible for the pessimistic performa... » read more

Blog Review: July 10
By Ed Sperling - 10 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster rolls out part four of his epic functional verification study, this one on design and verification reuse. If you work in the verification world, pounce. Cadence’s Brian Fuller looks back over a quarter century of technology—and what the average salary of a hardware design engineer will be in a 15 years: $499,000. But what will a cup of coffee cost?... » read more

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