tag: Mentor Graphics

The Power Of Standards
By Barry Pangrle - 08 Jul, 2010 - Comments: 0

By Barry Pangrle It’s often said that the wonderful thing about standards is that there are so many to choose from. As an industry, EDA seems to have a short memory as VMM and OVM (now becoming UVM), VHDL and Verilog, and more recently UPF and CPF. In cases where one standard suffices, it is horribly inefficient to create multiple “standards.” It is a waste of effort and resources for ED... » read more

The Power Of IP
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ann Steffora Mutschler As the number of design starts goes down the corresponding complexity of SoCs has gone up—and continues to grow. Everyone is looking at the value they can bring to the table as increasing proportions of SoCs are either reused from pre-existing IP within the company designing the chip or brought in from outside. Because is economically impractical to start an SoC... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

End User Report: EDA Industry Realignment
By Ann Mutschler - 24 Jun, 2010 - Comments: 0

By Ann Steffora Mutschler The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, ... » read more

The Future Of IP
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP. In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exac... » read more

The Tide Is Turning
By Jon McDonald - 24 Jun, 2010 - Comments: 0

By Jon McDonald I was at DAC last week. Over the course of the week I had a chance to talk with a significant number of customers and others in the industry. As has been the case the past few years there was good interest in system-level design. But from my perspective the tone of the discussions experienced a major shift this year. In the past, much of the discussion was around “why—wh... » read more

The Power Of The Customer Experience
By Barry Pangrle - 10 Jun, 2010 - Comments: 0

By Barry Pangrle Consumers of electronics don’t buy chips, they buy products or gadgets. Sure the geeks among us may know about “the chip” in a PC, typically in reference to the CPU or maybe even the GPU. But there are many chips in the product and you’d have to be an über-geek to know all of them. How many customers actually know the primary SoC in their smart phone? The point is ... » read more

Special Report: Using FPGAs For 3D Stacking
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

Corners Up, Margins Down
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC. The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on ... » read more

The Road To DAC: One On One With Wally Rhines
By Ed Sperling - 10 Jun, 2010 - Comments: 0

Mentor Graphics' CEO talks with Low-Power Engineering about the cost of designing a chip, the rising percentage of embedded software, the shift to FPGAs and what's changing in EDA. [youtube vid=Zjs9xz4iD3E] » read more

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