Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

BEOL Issues At 10nm And 7nm (part 2)

By Ed Sperling - 04 Jan, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Deeper Inside Intel

By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

ECOs and Multi-Patterning: It Can Be Done

By David Abercrombie - 21 Apr, 2016 - Comments: 0

By David Abercrombie and Alex Pearson A lot has been written and discussed about how to decompose (color) layouts for advanced process nodes that require multipatterning (MP). However, one topic that has been sorely ignored is how to efficiently make changes to designs that are already colored, or even taped out and processed. We tend to act like all designs work out the first time through... » read more

What Works After 7nm?

By Mark LaPedus - 20 Aug, 2015 - Comments: 3

An Steegen, senior vice president of process technology at [getentity id="22217" e_name="Imec"], the Belgium-based R&D organization, sat down with Semiconductor Engineering to discuss the future of process technology and transistor trends all the way to 3nm. SE: Some say the semiconductor industry is maturing. Yet we have more device types and options than ever before, right? Steegen:... » read more

Why DSA Is Cost Effective For 7nm And Below

By Yuansheng Ma - 30 Jul, 2015 - Comments: 0

The upcoming 7nm process node presents tough challenges both for printability and cost. At 7nm and below, multi-patterning is required, which makes the manufacturing process more expensive by requiring more masks. To control costs, any alternative technology that provides equivalent yields with fewer patterning steps should be explored. One promising option is to use directed self-assembly (... » read more

Here Comes 7nm

By Ed Sperling - 09 Jul, 2015 - Comments: 0

A consortium of companies involving IBM, GlobalFoundries and Samsung has rolled out the first 7nm test chip using silicon germanium as a substrate, using EUV to pattern multiple layers. While this doesn't mean the cost equation is even close to being solved, or that more than a handful of companies will push forward to that node anytime soon using SiGe as the substrate material, it does cre... » read more

Litho Challenges Break The Design-Process Wall

By Katherine Derbyshire - 22 Jun, 2015 - Comments: 3

The days when chip designers could throw tape “over the wall” to the manufacturing side are long gone. Over the last several technology generations, increasingly restrictive process kits have forced designers to accommodate their circuit structures to the manufacturing process. Lacking a successor to 193nm lithography, the industry has turned to increasingly complex resolution enhancemen... » read more

The Bumpy Road To 10nm FinFETs

By Mark LaPedus - 21 May, 2015 - Comments: 0

Foundry vendors are currently ramping up their 16nm/14nm [getkc id="185" kc_name="finFET"] processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process. Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm nod... » read more

Tech Talk: 14nm

By Ed Sperling - 21 May, 2015 - Comments: 0

Tamer Ragheb, digital design methodology technical lead at GlobalFoundries about what's changed with 14nm finFETs, including coloring with double patterning, new corners, Miller Effects, timing issues and variability. [youtube vid=Yk6jSKCtsjU] » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?