AI And High-NA EUV At 3/2/1nm

By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

EUV Challenges And Unknowns At 3nm and Below

By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Challenges Linger For EUV

By Mark LaPedus - 11 Nov, 2020 - Comments: 2

Mask/Lithography Issues For Mature Nodes

By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Finding Defects With E-Beam Inspection

By Mark LaPedus - 20 Aug, 2020 - Comments: 0

Several companies are developing or shipping next-generation e-beam inspection systems in an effort to reduce defects in advanced logic and memory chips. Vendors are taking two approaches with these new e-beam inspection systems. One is a more traditional approach, which uses a single-beam e-beam system. Others, meanwhile, are developing newer multi-beam technology. Both approaches have thei... » read more

Manufacturing Bits: June 8

By Mark LaPedus - 08 Jun, 2020 - Comments: 0

Maskless EUV lithography At this week’s 2020 EUVL Workshop, KJ Innovation will present more details about its efforts to develop a maskless extreme ultraviolet (EUV) lithography technology. Still in R&D, KJ Innovation’s maskless EUV technology involves a high-numerical aperture (high-NA) system with 2 million individual write beams. The 0.55 NA technology is targeted for direct-write l... » read more

Finding Defects In EUV Masks

By Mark LaPedus - 23 Jan, 2020 - Comments: 0

Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 20 Dec, 2019 - Comments: 0

Fab tools and materials In a blog, David Haynes, managing director of strategic marketing at Lam Research, talks about the IoT and automotive chip markets, which are fabricated at a wide range of technology nodes. Hoya recently made an unsolicited $1.4 billion bid to acquire NuFlare, a supplier of e-beam mask writers and other equipment. Click here for more information. Hoya makes several p... » read more

Making And Protecting Advanced Masks

By Mark LaPedus - 27 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Inspecting, Patterning EUV Masks

By Mark LaPedus - 06 Nov, 2019 - Comments: 0

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?