Mask Making Issues With EUV

By Mark LaPedus - 17 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

Curvilinear Full-Chip ILT

By Ed Sperling - 17 Oct, 2019 - Comments: 0

Leo Pang, chief product officer and executive vice president at D2S, talks about the speed improvements with full-chip inverse lithography technology, why it is so critical in stitching together large chips, and how this approach differs from traditional litho approaches. » read more

EUV Mask Readiness Challenges

By Mark LaPedus - 21 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography and photomask technologies with Emily Gallagher, principal member of the technical staff at Imec; Harry Levinson, principal at HJL Lithography; Chris Spence, vice president of advanced technology development at ASML; Banqiu Wu, senior director of process development at Applied Materials; and Aki Fujimura, chief ... » read more

Finding Defects In Chips With Machine Learning

By Mark LaPedus - 12 Mar, 2019 - Comments: 7

Chipmakers are using more and different traditional tool types than ever to find killer defects in advanced chips, but they are also turning to complementary solutions like advanced forms of machine learning to help solve the problem. A subset of artificial intelligence (AI), machine learning has been used in computing and other fields for decades. In fact, early forms of machine learning ha... » read more

Multi-Beam Mask Writing Finally Comes Of Age

By Mark LaPedus - 15 Nov, 2018 - Comments: 0

Elmar Platzgummer, chief executive of IMS Nanofabrication, sat down with Semiconductor Engineering to discuss photomask and mask writing trends. IMS, a subsidiary of Intel, is a supplier of multi-beam e-beam systems for photomask production. What follows are excerpts of that conversation. SE: For years, photomask makers have used single-beam e-beam tools to pattern or write the features on ... » read more

Fabs Meet Machine Learning

By Mark LaPedus - 19 Jul, 2018 - Comments: 2

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to discuss Moore’s Law and photomask technology. Fujimura also explained how artificial intelligence and machine learning are impacting the IC industry. What follows are excerpts of that conversation. SE: For some time, you’ve said we need more compute power. So we need faster chips at advanced nodes, but cost... » read more

Next-Gen Mask Writer Race Begins

By Mark LaPedus - 19 Oct, 2017 - Comments: 5

Competition is heating up in the mask writer equipment business as two vendors—Intel/IMS and NuFlare—vie for position in the new and emerging multi-beam tool segment. Last year, Intel surprised the industry by acquiring IMS Nanofabrication, a multi-beam e-beam mask writer equipment vendor. Also last year, IMS, now part of Intel, began shipping the world’s first multi-beam mask writer f... » read more

Challenges Mount For Photomasks

By Mark LaPedus - 21 Sep, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss photomask technologies with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); Banqiu Wu, principal member of the technical staff and chief technology officer of the Mask and TSV Etch Division at [getentity id="22817" e_name="Applied Materials"]; Weston Sousa, general manager of the Reticle Products Division at [getentity id="22876" commen... » read more

Big Changes In Patterning

By Ed Sperling - 22 Feb, 2017 - Comments: 0

Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV's future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design. SE: Patterning issues are getting a lot of attention at 10nm and 7n... » read more

Battling Fab Cycle Times

By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

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Knowledge Centers
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