Speeding Up Process Optimization With Virtual Processing

By Coventor - 16 Jul, 2020 - Comments: 0

Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patterning and foot print scaling issues. Unique integration and patterning schemes have b... » read more

Speeding Up Verification Using SystemC

By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Why Pinpoint Accuracy Is Important When Monitoring Conditions On Chip

By Ramsay Allen - 11 Jan, 2018 - Comments: 0

A Q&A with Moortec CTO Oliver King. Why is there an increasing requirement for monitoring on chip? Since the beginning of the semiconductor industry, we have relied on a doubling of transistor count per unit area every 18 months as a way to increase performance and functionality of devices. Since 28nm, this has broken. As such, designers now need to find new ways to continue increasing... » read more

Reality Check: A Guide To Understanding Optimized Processor Cores

By Synopsys - 11 Mar, 2015 - Comments: 0

The performance of the processor core in an SoC is often a key product differentiator. It's not just about performance though - power and cost are equally important considerations. In today's markets, SoC developers have to hit aggressive power, performance and area goals to remain competitive. This white paper discusses the many interacting parameters that determine the optimum implementation ... » read more

FinFET And Multi-Patterning Aware Place And Route Implementation

By Mentor, a Siemens Business - 21 May, 2014 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To view this white paper, click here. » read more

Flexibility Improves Memory Interface Bandwidth

By Ann Mutschler - 10 Oct, 2013 - Comments: 0

In today’s SoCs, memory is the heart or at least one of the main elements of the design. As such, designing them carefully is paramount to achieving the best bandwidth, performance and power. Performance is very important to be able to access the memory and to trade and store information from different IPs with shared memories or local memories. From the power perspective, every access to... » read more

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The critical, and growing, significance of mature node chips and processes.

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Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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by Brian Bailey

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tag: optimization

Speeding Up Process Optimization With Virtual Processing

Speeding Up Verification Using SystemC

Why Pinpoint Accuracy Is Important When Monitoring Conditions On Chip

Reality Check: A Guide To Understanding Optimized Processor Cores

FinFET And Multi-Patterning Aware Place And Route Implementation

Flexibility Improves Memory Interface Bandwidth

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