tag: parasitics

Signoff-Accurate Partial Layout Extraction And Early Simulation
By Soni Kapoor - 11 Aug, 2022 - Comments: 0

It is a rewarding experience for EDA developers and users to collaborate on deploying advanced techniques to improve design productivity. This blog will describe the experience of collaborating with customers on a new technology for reducing the number of analog design iterations. Analog design requires that engineers balance the needs to 1) reach market quickly 2) deliver high quality 3) at lo... » read more

Parasitic Characterization Comes To Power Design Simulation
By Don Dingee - 09 Mar, 2022 - Comments: 0

Two power design challenges are taking teams into unfamiliar territory. Wide bandgap (WBG) semiconductors target greater efficiency and density. Stricter EMI compliance regulations now come standard in mission-critical industries. Power design practices are still catching up. Simulation often takes a back seat to respinning hardware prototypes until success. What’s missing that could make sim... » read more

Dynamic in-chip current distribution simulation technology for power device layout design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

Faster Analog Design Closure With Early Parasitic Analysis Flow – Part 1
By Synopsys - 22 Sep, 2021 - Comments: 0

In part 1 of this series, Denis Goinard, Director of Engineering at Synopsys, discusses how Synopsys provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence. Click here to play the video. Note: This is a Synopsys 'video white paper.' For more video white papers, click h... » read more

3 Types Of AI Hardware
By Ed Sperling - 20 Jul, 2020 - Comments: 1

As AI chips become more pervasive, three primary approaches are moving to the forefront. Bradley Geden, director of product marketing at Synopsys, looks at how to take advantage of repeatability, what the different flavors look like, the difference between flat and hierarchical design, and what impact black-box arrays have on programmability. » read more

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification
By Greg Curtis - 25 Jun, 2020 - Comments: 0

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

Low-Power Analog
By Brian Bailey - 14 May, 2020 - Comments: 3

Analog circuitry is usually a small part of a large SoC, but it does not scale in the same way as digital circuitry under Moore's Law. The power consumed by analog is becoming an increasing concern, especially for battery-operated devices. At the same time, little automation is available to help analog designers reduce consumption. "Newer consumer devices, like smartphones and wearables, alo... » read more

Earlier Is Better In Latch-Up Detection
By Flint Yoder - 13 Feb, 2020 - Comments: 1

Physical verification is an essential step in integrated circuit (IC) design verification. Foundries provide design rule manuals that specify the precise physical requirements needed to ensure the design can be correctly manufactured, and the verification team runs the layout through checks based on those rules to ensure compliance. However, ensuring that a design can be manufactured does not g... » read more

Interconnect Inductance Extraction For Analog And RF IC Designs
By Mentor, a Siemens Business - 12 Feb, 2020 - Comments: 0

Increasing operating frequencies for analog/RF designs mean interconnect inductance parasitic extraction is now required to ensure accurate circuit performance and high reliability. Automated field solver-based inductance extraction of both self and mutual parasitics enables IC companies to deliver analog/RF chips that provide the intended level of performance and reliability. To read more, ... » read more

Analog Simulation At 7/5/3nm
By Ed Sperling - 27 Jan, 2020 - Comments: 0

Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip. » read more

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