Optimize Physical Verification Cost Of Ownership

By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Early Detection Of Power/Ground Shorts Speeds Time To Tapeout

By Mentor, a Siemens Business - 27 May, 2020 - Comments: 0

Early detection of power/ground shorts lets design teams fix errors during implementation, avoiding time-consuming design data merging and full-chip physical verification. The Calibre platform provides fast, automated power/ground checking using abstract LEF/DEF input, significantly reducing the time and resources needed to ensure these violations are removed prior to tapeout. To read more, ... » read more

Physical Verification For Photonics Integrated Circuits

By Manoz Palaparthi - 26 Mar, 2020 - Comments: 0

Silicon photonics is a promising solution for the explosive growth of data volume and network traffic in computing and communications. Silicon photonics integrates photonics applications on a silicon wafer, utilizing mainstream Si-based technology. Photonics integrated circuits (PIC) offer several advantages over traditional integrated circuits: faster data transfer speeds, lower power consumpt... » read more

Fast-Track Your Early SoC Design Exploration And Verification

By Nermeen Hossam - 26 Sep, 2019 - Comments: 0

By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

The Growing Uncertainty Of Sign-Off At 7/5nm

By Ann Mutschler - 09 May, 2019 - Comments: 3

Having enough confidence in designs to sign off prior to manufacturing is becoming far more difficult at 7/5nm. It is taking longer due to increasing transistor density, thinner gate oxides, and many more power-related operations that can disrupt signal integrity and impact reliability. For many years, designers have performed design rule checks as part of physical verification of the desi... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability

By Sherif Hany - 25 Apr, 2019 - Comments: 0

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

Verification At 7/5nm

By Ed Sperling - 25 Apr, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

Chip Design For The Age Of New Mobility

By Andrew Macleod - 07 Mar, 2019 - Comments: 0

In the new age of mobility, vehicles are valued more and more for their electronic features instead of mechanical specifications. As a result, companies that are able to own and optimize the design of these critical electronics will capture more of the available profit. This is bringing traditional automotive manufacturers into the electronics business, while simultaneously attracting tech comp... » read more

Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction Results

By Yousry ElMaghraby - 20 Dec, 2018 - Comments: 0

There comes a time at every foundry and IC design company when it becomes necessary to run a correlation between a rule-based parasitic extraction (PEX) table and a field solver solution. And when that time arrives, there are a few (five, to be precise) details that will help ensure the correlation produces accurate results. But before we get to those, let’s do a quick refresh on PEX techniqu... » read more

A New Approach To Resistance Extraction For Unconventional Geometries

By Hossam Sarhan - 13 Dec, 2018 - Comments: 0

Unconventional metal structures have begun popping up in integrated circuits (ICs) with increasing regularity, for a number of reasons. The growing demand for integrated cameras and image recognition capabilities has fueled the need for components such as high-quality CMOS image sensors with low noise, high dynamic range, and low power. Technology scaling has also contributed to an increase in ... » read more

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tag: physical verification