tag: RISC-V

RISC-V decoupled Vector Processing Unit (VPU) For HPC
By Technical Paper Link - 20 Dec, 2022 - Comments: 0

A technical paper titled "Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications" was published by researchers at Barcelona Supercomputing Center, Spain. "The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of ... » read more

Efficient Trace In RISC-V
By Ed Sperling - 19 Dec, 2022 - Comments: 0

Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what's needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are tak... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

Manage Your Risk In RISC-V
By Peter Shields - 06 Dec, 2022 - Comments: 0

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making broad adoption of RISC-V possible, and one example is the introduction of efficient trace for RISC-V cores. When incorp... » read more

Capability Hardware Enhanced RISC Instructions (CHERI) For Verification, With Better Memory Safety (Oxford)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "A Formal CHERI-C Semantics for Verification" was published by researchers at University of Oxford. Abstract: "CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, ... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows
By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

RISC-V Is Thriving: Here’s What You Need to Know
By Steve Brown - 03 Nov, 2022 - Comments: 0

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set Computer, meaning it’s designed to simplify each individual instruction given to the computer. As RISC-V is an open standard, anyone can implement, customize, and expand the ISA to suit their r... » read more

Side-Channel Secure Translation Lookaside Buffer Architecture
By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A new technical paper titled "Risky Translations: Securing TLBs against Timing Side Channels" was posted by researchers at Ruhr University Bochum (Germany) and Cyber-Physical Systems of the German Research Center for Artificial Intelligence (DFKI). Abstract: "Microarchitectural side-channel vulnerabilities in modern processors are known to be a powerful attack vector that can be utilized to... » read more

Bug-Free Designs
By Brian Bailey - 27 Oct, 2022 - Comments: 0

It is possible in theory to create a design with no bugs, but it's impractical, unnecessary, and extremely difficult to prove for bugs you care about. The problem is intractable because the potential state space is enormous for any practical design. The industry has devised ways to handle this complexity, but each has limitations, makes assumptions, and employs techniques that abstract the p... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy