Help, 3D-IC Is Stuck In A Country Song

By John Ferguson - 30 Nov, 2023 - Comments: 0

Every time I focus on three-dimensional (3D) integrated circuit (IC) design, I start hearing the Luke Bryan song “Rain Makes Corn, Corn Makes Whiskey.” Not because I need a strong drink to work with 3D-IC designs, but because there is a similar, although slightly more complicated, series of cause and effect issues that impact 3D-ICs. Pushing electrons through very thin metal wires and switc... » read more

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach

By Siemens EDA - 30 Nov, 2023 - Comments: 0

3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

Making Heterogeneous Integration More Predictable

By Ed Sperling - 29 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss problems and potential solutions in heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom I... » read more

Blog Review: November 29

By Jesse Allen - 29 Nov, 2023 - Comments: 0

Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

Blog Review: November 15

By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

What Can Go Wrong In Heterogeneous Integration

By Ed Sperling - 15 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom IC & PCB Group; and Tony Mastroia... » read more

DRAM Choices Are Suddenly Much More Complicated

By Ed Sperling - 13 Nov, 2023 - Comments: 0

Chipmakers are beginning to incorporate multiple types and flavors of DRAM in the same advanced package, setting the stage for increasingly distributed memory but significantly more complex designs. Despite years of predictions that DRAM would be replaced by other types of memory, it remains an essential component in nearly all computing. Rather than fading away, its footprint is increasing,... » read more

Flipping Processor Design On Its Head

By Ann Mutschler - 09 Nov, 2023 - Comments: 2

AI is changing processor design in fundamental ways, combining customized processing elements for specific AI workloads with more traditional processors for other tasks. But the tradeoffs are increasingly confusing, complex, and challenging to manage. For example, workloads can change faster than the time it takes to churn out customized designs. In addition, the AI-specific processes may ex... » read more

An Entangled Heterarchy

By Brian Bailey - 09 Nov, 2023 - Comments: 1

For decades, a form of structural hierarchy has been the principal means of handling complexity in chip design. It's not always perfect, and there is no ideal way in which to divide and conquer because that would need to focus on the analysis being performed. In fact, most systems can be viewed from a variety of different hierarchies, equally correct, and together forming a heterarchy. The e... » read more

SRAM In AI: The Future Of Memory

By Karen Heyman - 09 Nov, 2023 - Comments: 0

Experts at the Table — Part 1: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part two of this conversation can be found here and part three is here. [L-R]: ... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Siemens EDA

Help, 3D-IC Is Stuck In A Country Song

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach

Making Heterogeneous Integration More Predictable

Blog Review: November 29

Blog Review: November 15

What Can Go Wrong In Heterogeneous Integration

DRAM Choices Are Suddenly Much More Complicated

Flipping Processor Design On Its Head

An Entangled Heterarchy

SRAM In AI: The Future Of Memory

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