Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster

By Kesmat Shahin - 23 Feb, 2023 - Comments: 0

Designers everywhere know that with the increasing complexity of integrated circuits (ICs), meeting tapeout schedules has become increasingly difficult. While there are often many reasons for missing tapeouts, one critical component is the significant amount of time needed to run the signoff layout verification cycle, which contributes to overall signoff process duration. Much of this schedule ... » read more

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking

By Siemens EDA - 22 Feb, 2023 - Comments: 0

Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows that require correct connectivity for valid results. The Calibre nmLVS Recon tool targets essential and relevant early-stage circuit verification pain points, such as electrical rule checking (ERC) ... » read more

Blog Review: Feb. 22

By Jesse Allen - 22 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster observes that the FPGA market continues to go through a similar complexity curve that the IC/ASIC market experienced in the early and mid-2000 timeframe. Synopsys' Mitch Heins explores the benefits of heterogeneous integration of lasers and active gain elements in a silicon-based photonic IC, including reduced system costs, size, weight, and power along with improv... » read more

Managing Thermal-Induced Stress In Chips

By Karen Heyman - 16 Feb, 2023 - Comments: 0

At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Blog Review: Feb. 15

By Jesse Allen - 15 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster examines the relationship between verification maturity and non-trivial bug escapes into production, as well as whether safety critical development processes yield higher quality in terms of preventing bugs and achieving silicon success. Synopsys' Shankar Krishnamoorthy finds that the rapid progress of machine learning models is driving demand for more domain-speci... » read more

Chiplets Taking Root As Silicon-Proven Hard IP

By Ann Mutschler - 09 Feb, 2023 - Comments: 0

Chiplets are all the rage today, and for good reason. With the various ways to design a semiconductor-based system today, IP reuse via chiplets appears to be an effective and feasible solution, and a potentially low-cost alternative to shrinking everything to the latest process node. To enable faster time to market, common IP or technology that already has been silicon-proven can be utilized... » read more

Everything, Everywhere, All At Once: Big Data Reimagines Verification Predictability And Efficiency

By Darron May - 09 Feb, 2023 - Comments: 0

Big data is a term that has been around for many years. The list of applications for big data are endless, but the process stays the same: capture, process and analyze. With new, enabling verification solutions, big data technologies can improve your verification process efficiency and predict your next chip sign-off. By providing a big data infrastructure, with state-of-the-art technologies... » read more

Improving Verification Predictability And Efficiency Using Big Data

By Siemens EDA - 08 Feb, 2023 - Comments: 0

Big data is a term that has been around for decades. It was initially defined as data sets captured, managed, and processed in a tolerable amount of time beyond the ability of normal software tools. The only constant in big data’s size over this time is that it’s been a moving target driven by improvements in parallel processing power and cheaper storage capacity. Today most of the industry... » read more

Blog Review: Feb. 8

By Jesse Allen - 08 Feb, 2023 - Comments: 0

Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics

By Ed Sperling - 08 Feb, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Siemens EDA

Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking

Blog Review: Feb. 22

Managing Thermal-Induced Stress In Chips

Blog Review: Feb. 15

Chiplets Taking Root As Silicon-Proven Hard IP

Everything, Everywhere, All At Once: Big Data Reimagines Verification Predictability And Efficiency

Improving Verification Predictability And Efficiency Using Big Data

Blog Review: Feb. 8

Big Changes Ahead For Chip Technology And Industry Dynamics

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Knowledge Centers
Entities, people and technologies explored