tag: Siemens

Rethinking Your Approach To Radiation Mitigation
By Mentor, a Siemens Business - 03 Jun, 2020 - Comments: 0

Formal verification and automation provide an effective, high quality, and repeatable process for fault analysis, protection, and verification for FPGA designs used in high radiation environments. This paper describes an automated systematic approach based on formal verification structural and static analysis that identifies design susceptibility to radiation induced faults. To read more, clic... » read more

Blog Review: June 3
By Jesse Allen - 03 Jun, 2020 - Comments: 0

Cadence's Paul McLellan takes a look at how Ethernet came to dominate wired networking and is now taking on automotive to provide the bandwidth necessary for the increasing number of sensors in modern vehicles. Mentor's Colin Walls notes the difficulty of assessing the quality of software, some key areas to pay attention to when assessing quality or trying to write quality code, and the bottom... » read more

(Artificially) Intelligent Verification
By Brian Bailey - 01 Jun, 2020 - Comments: 1

Functional verification produces a lot of data, , but does that make it suitable for Artificial Intelligence (AI) or Machine Learning (ML)? Experts weigh in about where and how AI can help and what the industry could do to improve the benefits. "It's not necessarily the quantity," says Harry Foster, chief scientist for verification at Mentor, a Siemens Business. "It's the quality that matter... » read more

Lower Resistance Protects Against Failure In IC Design
By Fady Fouad - 28 May, 2020 - Comments: 0

By Fady Fouad, Esraa Swillam, and Jeff Wilson When you’re fighting off a threat, you typically want all the resistance you can muster. In IC design, on the other hand, minimizing resistance is crucial to success in power structure design. As metals get narrower with technology node advances, resistance levels rise, and voltage drop (IR) and electromigration (EM) issues grow, both in number... » read more

Early Detection Of Power/Ground Shorts Speeds Time To Tapeout
By Mentor, a Siemens Business - 27 May, 2020 - Comments: 0

Early detection of power/ground shorts lets design teams fix errors during implementation, avoiding time-consuming design data merging and full-chip physical verification. The Calibre platform provides fast, automated power/ground checking using abstract LEF/DEF input, significantly reducing the time and resources needed to ensure these violations are removed prior to tapeout. To read more, ... » read more

The Good And Bad Of Chiplets
By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2020 - Comments: 0

Mentor's Neil Johnson takes a look at achieving a practical verification methodology starting with an exclusively constrained random flow and building up by adding techniques and gauging the consequences. Cadence's Paul McLellan explains the history of neural networks and how we've been trying to mimic the brain for decades, only to see funding dry up until a sudden resurgence of annotated i... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 May, 2020 - Comments: 0

Tools & IP Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIP... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2020 - Comments: 0

Synopsys' Jonathan Knudsen demystifies fuzzing techniques and why the process of sending targeted, intentionally invalid data is important to determining security. Mentor's Chris Spear explains both the potential benefits and challenges of the UVM Configuration Database and guidelines to improve performance. Cadence's Paul McLellan continues the look back at mobile history with the beginn... » read more

Power Management And Integration Of IPs In SoCs: Part 2
By Progyna Khondkar - 14 May, 2020 - Comments: 0

Most IP are available as either soft or hard macros. But both pose immense challenges. This is especially so when integrating them into low power designs and conducting power aware (PA) verification, because the majority of IP are self-contained and pre-verified at the block level and they must be preserved in their entirety when integrated or verified in the SoC level. Part one of this two ... » read more

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