tag: simulation

Simulation Workflow For Efficiency Calculation Of A High-Performance Electric Powertrain
By Ansys - 08 Dec, 2021 - Comments: 0

In battery electric vehicles the efficiency of the powertrain has a big impact on driving range and performance. As the overall efficiency of the electric powertrain is typically more than 90%, further optimization is challenging. Especially in high-performance electric vehicles, the efficiency over one or multiple laps on a racing track is crucial. It requires accurate estimation of power loss... » read more

Advanced Packaging Shifts Design Focus To System Level
By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

Gaps In The AI Debug Process
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When an AI algorithm is deployed in the field and gives an unexpected result, it's often not clear whether that result is correct. So what happened? Was it wrong? And if so, what caused the error? These are often not simple questions to answer. Moreover, as with all verification problems, the only way to get to the root cause is to break the problem down into manageable pieces. The semico... » read more

Simulation-Based Fault Analysis for Resilient System-On-Chip Design
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover,... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

Debugging Embedded Applications
By Ann Mutschler - 10 Nov, 2021 - Comments: 0

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

What’s Missing For Designing Chips At The System Level
By Ed Sperling - 01 Nov, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Research on Wire Sweep of Integrated Circuit Packaging Based on Three-dimensional Flow Simulation
By Technical Paper Link - 31 Oct, 2021 - Comments: 0

Abstract: "Semiconductor manufacturing technology is becoming more and more rapidly. In the process of Integrated Circuit (IC) encapsulation, when wires contact each other, it will cause short circuit. Wire sweep has become the main factor affecting the reliability of the product. Therefore, it is a great challenge to master wire sweep in IC packaging process. This paper takes Low Profile Fi... » read more

What’s Next For Emulation
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

Materials and Device Simulations for Silicon Qubit Design and Optimization
By Technical Paper Link - 27 Oct, 2021 - Comments: 0

Abstract: "Silicon-based microelectronics technology is extremely mature, yet this profoundly important material is now also poised to become a foundation for quantum information processing technologies. In this article, we review the properties of silicon that have made it the material of choice for semiconductor-based qubits with an emphasis on the role that modeling and simulation have play... » read more

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