tag: SoCs

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

Exhaustive Verification of Reset Domain Crossings
By Synopsys - 08 Apr, 2020 - Comments: 0

It is difficult to imagine an aspect of semiconductor development more fundamental than reset. The ability to initialize the entire hardware design and clean all software running through a system-on-chip (SoC) is essential. Stating with a known state avoids propagation of signals with unknown values. Despite the best efforts at verification, lingering corner case bugs may put a system into a st... » read more

Changes In AI SoCs
By Ed Sperling - 12 Feb, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at ArterisIP, talks about the tradeoffs in AI SoCs, which range from power and performance to flexibility, depending on whether processing elements are highly specific or more general, and the need for more modeling of both hardware and software together. » read more

Week In Review: IoT, Security, Autos
By SE Staff - 24 Jan, 2020 - Comments: 0

AI/Edge Vastai Technologies is using Arteris IP’s FlexNoC Interconnect IP and AI Package for its Artificial Intelligence Chips for artificial intelligence and computer vision systems-on-chip (SoCs). Startup Vastai Technologies was founded in December 2018, designs ASICs and software platforms for computer vision and AI applications, such as smart city, smart surveillance, smart education, ac... » read more

A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform
By Synopsys - 11 Dec, 2019 - Comments: 0

It's a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today's large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal... » read more

CXL Vs. CCIX
By Ed Sperling - 06 Dec, 2019 - Comments: 0

Kurt Shuler, vice president of marketing at ArterisIP, explains how these two standards differ, which one works best where, and what each was designed for. » read more

Verdi Transaction Debug Solution: Unified Performance Analysis And Debug For Interconnect
By Synopsys - 13 Nov, 2019 - Comments: 0

In modern systems on chip (SoCs), where Arm AMBA protocols are intensively used as standard intellectual property (IP) interfaces, the interconnect is usually required to bridge and facilitate the communication between many different IP interfaces. The interconnect presents one of the biggest challenges of SoC verification, considering the different kinds of protocol interfaces, conversion of d... » read more

ML, Edge Drive IP To Outperform Broader Chip Market
By Kevin Fogarty - 03 Oct, 2019 - Comments: 0

The market for third-party semiconductor IP is surging, spurred by the need for more specific capabilities across a wide variety of markets. While the IP industry is not immune to steep market declines in semiconductor industry, it does have more built-in resilience than other parts of the industry. Case in point: The top 15 semiconductor suppliers were hit with an 18% decline in 2019 first-... » read more

Assuring the Integrity of RISC-V Cores and SoCs
By OneSpin Solutions - 21 Aug, 2019 - Comments: 0

The open RISC-V processor architecture is shaking up the intellectual property (IP) and system-on-chip (SoC) worlds. There is great interest and much industry activity underway. However, successful RISC-V core providers will have to verify all aspects of integrity for their designs: functional correctness, safety, security, and trust. SOC developers evaluating potential RISC-V need to check tha... » read more

Multiphysics Simulations For RFICs And SoCs For 5G Applications
By Ansys - 07 Aug, 2019 - Comments: 0

System-on-chips (SoCs) and radio frequency integrated circuits (RFICs) for 5G smartphones and networks need to manage huge amounts of antenna data and offer significantly high processing capabilities in thermally and power-constrained environments. ANSYS multiphysics simulations simultaneously solve power, thermal, variability, timing, electromagnetics and reliability challenges across the spec... » read more

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