tag: stacked die

The Final Deadline For EUV
By Ed Sperling - 27 Feb, 2014 - Comments: 5

When TSMC disclosed this week—in a public forum—that its production EUV lithography test had failed in one of the early test runs due to a power source issue, there were very different reactions. EUV, after all, is an emotional issue with billions of dollars invested and lots of jobs riding on this technology. To begin with, there has been the usual spin control. The message essentially ... » read more

Evolution Vs. Revolution
By Ann Mutschler - 27 Feb, 2014 - Comments: 1

In the electronic design automation industry changes to tools and flows are nearly always evolutionary. They hide as much change from the user as possible, allowing easier justification from an ROI perspective, and they raise far fewer objections from users, who don’t have to spend time learning how to use new technology or rethink tried and true approaches to problems. Revolution in chip ... » read more

Plug-And-Play Test Strategy For 3D ICs
By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

Are Processors Running Out Of Steam?
By Ed Sperling - 24 Feb, 2014 - Comments: 1

Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

Many Stresses Impact TSVs
By Ann Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

Can We Ever Agree On Moore’s Law?
By Ed Sperling - 13 Feb, 2014 - Comments: 0

Nearly five decades after Moore’s Law was first introduced—the famous observation turns 50 next year—we’re still debating it. There are disagreements about whether it was an economic or technology statement. There are questions about whether it was really every 24 months or every 18 months—it was actually both. And there are questions about which companies it really applied to and who... » read more

Tech Talk: Power, Performance And Area In 2.5D
By Ed Sperling - 12 Feb, 2014 - Comments: 2

The cost will be comparable at first, but the only way to improve power, performance AND area at the same time will be with a different architectural approach. [youtube vid=XAbE7jpjuMA] » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 27 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As an industry we’ve got a pretty good grasp ... » read more

The Road Ahead for 2014: Semiconductors
By Brian Bailey - 23 Jan, 2014 - Comments: 1

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 06 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: The future of technology isn’t just about technology. It’s about people and regulations, as well. Where are the hurdles ... » read more

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