SiPs: The Best Things in Small Packages

By Laura Peters - 20 Oct, 2022 - Comments: 0

System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

Heterogeneous Integration Co-Design Won’t Be Easy

By Tom Beckley - 13 Oct, 2022 - Comments: 0

The days of “throwing it over the wall” are over. Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core—one that lives or dies on seamless interaction between your analog and digital IC and package design teams. Heterogeneous integration is the use of advanced packaging technologies to combine smaller, discrete chiplets into one syste... » read more

Thermal Simulation Of DSMBGA And Coupled Thermal-Mechanical Simulation Of Large Body HDFO

By Nathan Whitchurch - 15 Sep, 2022 - Comments: 0

Electronic packaging has continued to become more complex with higher device count, higher power densities and Heterogeneous Integration (HI) becoming more common. In the mobile space, systems that were once separate components on a printed circuit board (PCB) have now been relocated along with all their associated passive devices and interconnects into single System in Package (SiP) style suba... » read more

Enabling The 5G RF Front-End Module Evolution With The DSMBGA Package

By Amkor - 21 Jul, 2022 - Comments: 0

The advanced SiP double-sided molded BGA platform has become an industry technology standard in this domain. Applying leading-edge design rules for 3D component placement and double-sided molding, together with conformal and compartmental shielding and in-line RF testing, delivers integration levels in a small form factor with high yield. In addition to formidable SiP capacity and DSMBGA techno... » read more

SiPs And MCMs Broaden Opportunities For Military-Aerospace System Design

By Rosie Medina - 23 May, 2022 - Comments: 0

Military and aerospace (mil-aero) applications, from satellites and rockets to ships and planes, increasingly require electronic systems and subsystems with high functionality and performance in a small form factor. Meeting these demands poses higher-level challenges for packaging of these microelectronic devices, which needs to be rugged, long-lived, and affordable. Usage of multi-chip modu... » read more

Unintended Coupling Issues Grow

By Brian Bailey - 24 Feb, 2022 - Comments: 0

The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably. Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go... » read more

Warpage Of Compression Molded SiP Strips

By JCET - 17 Feb, 2022 - Comments: 0

By Eric Ouyang, Yonghyuk Jeong, JaeMyong Kim, JaePil Kim, OhYoung Kwon, and Michael Liu of JCET; and Susan Lin, Jenn An Wang, Anthony Yang, and Eric Yang of CoreTech System (Moldex3D). Abstract System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing p... » read more

Advanced Packaging Shifts Design Focus To System Level

By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

The New Technology Solutions For Advanced SiP Devices

By YongJai Seo - 18 Nov, 2021 - Comments: 0

For many years, System-in-Package (SiP) technology has been a focus for semiconductor packaging to address the ongoing market trend of system integration and size reduction. Today’s increased complexity and higher package density for SiP devices has driven the development of new packaging technologies. In response, compartmental shield technology makes it possible to put several functions int... » read more

A Broad Look Inside Advanced Packaging

By Mark LaPedus - 18 Nov, 2021 - Comments: 0

Choon Lee, chief technology officer of JCET, sat down with Semiconductor Engineering to talk about the semiconductor market, Moore’s Law, chiplets, fan-out packaging, and manufacturing issues. What follows are excerpts of that discussion. SE: Where are we in the semiconductor cycle right now? Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. ... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: system in package