Inside The Package

By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house. SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for year... » read more

3 Ways To Differentiate

By Ed Sperling - 13 Jan, 2013 - Comments: 0

Time-to-market pressures and complexity have put the squeeze on design teams. They have to bring incredibly complex SoCs to market on time, make sure they’re functionally correct and work within a tight power budget, and they have to come in on or under budget. Amazingly, they’re still able to accomplish this, thanks to some heroic efforts on the part of engineers and some incredible adv... » read more

What’s Before Stacked Die?

By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production. In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current ... » read more

Mobile Memory Madness

By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap. As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architectur... » read more

Deep Inside Intel

By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Mark Bohr, senior fellow at Intel, to talk about a wide range of manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends. SMD: Will EUV make 10nm? And if it doesn’t, what effect will that have on Intel? Bohr: For a process module as critical as lithography... » read more

ASMC: TSVs Needed as Scaling Challenges Mount

By Ed Sperling - 29 May, 2012 - Comments: 0

By David Lammers With the industry facing challenges in the introduction of EUV lithography and high costs for double patterning, TSV introductions have taken on heightened importance, participants said at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC), held in Saratoga Springs, N.Y. in mid-May. Risto Puhakka, president of market research firm VLSI Research Inc., said the g... » read more

Bigger Shifts Ahead

By Ed Sperling - 29 May, 2012 - Comments: 0

At 130nm the manufacturing portion of the semiconductor industry struggled with copper interconnects, 300mm wafers and immersion lithography. At 20nm and 14nm it will have to grapple with double, triple and possibly even quadruple patterning, new gate structures, the usual increases in process variation, far more expensive designs, complex challenges in attaining reasonable yields and in connec... » read more

The Brave New World Of Modeling TSVs

By Ed Sperling - 26 May, 2012 - Comments: 0

By Ann Steffora Mutschler With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together... » read more

New Processes Define New Power Plans

By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Pallab Chatterjee FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design. At ISQED, Robert Geer, chief academic officer at the College of Nanosca... » read more

3D DRAM Makers Inch Closer To Production

By Ed Sperling - 01 Dec, 2011 - Comments: 0

By Mark LaPedus For some time, DRAM makers have been developing 3D memory chips, but commercial products still are not due out for some time because of technical and cost issues. But the advent of the 3D DRAM era could be near the turning point, as two memory rivals have separately moved to bring their respective technologies closer to production. In one move, Micron Technology Inc. has di... » read more

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