The Bumpy Road To FinFETs

The shift from planar transistors to finFETs is a major inflection point in the IC industry. FinFETs are expected to enable higher performance chips at lower voltages. And the next-generation transistor technology also could allow the industry to extend CMOS to the 10nm node and perhaps beyond.

But as it turns out, finFET technology is also harder to master than previously thought. For example, most, if not all, leading-edge foundries are currently grappling with yield and other issues with finFETs in the fab right now, causing various glitches in their respective production ramps, according to one semiconductor equipment maker.

Case in point: Intel recently delayed the production ramp of its second-generation finFET process at 14nm, citing yield issues as the cause. Meanwhile, GlobalFoundries, TSMC, Samsung and UMC separately plan to move into mass production with their initial 16nm/14nm finFET processes sometime in 2015, although there are already rumblings that vendors could experience some hiccups along the way.

“Now, in logic and foundry, with the introduction of the new 3D gate architectures, the yield issues our customers are grappling with today are proving to be the most challenging that the industry has ever faced and even the smallest variation in process margin can cause significant yield losses for these devices,” said Rick Wallace, president and chief executive of KLA-Tencor, in a recent conference call. “In the significant yield challenges the market leaders have encountered in (the) early development of the 16-, 14- and 10-nanometer nodes have created uncertainty over timing of these transitions in calendar year 2014.”

In fact, there are several things that could go wrong with finFETs, whether that’s in the design flow or in the fab. In the fab, for example, there are 30% to 40% more process steps at the sub-20nm nodes, as compared to 28nm. This, in turn, increases the chances of more killer defects entering in the flow.

“I would not expect a perfect finFET rollout,” said Joanne Itow, an analyst with Semico Research. “FinFETs are not an easy thing to do. There are issues cropping up, whether it’s new materials or the designs themselves.”

Needless to say, the foundries are working hard to solve the issues in the fab. Meanwhile, foundry customers hope to ship finFET-based chips sooner than later. And so, many foundry customers are asking themselves a simple question: What’s the holdup, or potential issues, with finFETs in the fab?

As it turns out, there are a number of challenging process steps, or choke points, for finFETs as well as the 16nm/14nm and 10nm processes in general. Generally, in no particular order, patterning, etch, interconnects and process control are arguably the most difficult.

Some foundry customers are already familiar with the issues. Many others are just getting their arms around the problems. All customers will need to get a handle on the manufacturing issues in order to have more realistic expectations about their design schedules.

Why finFETs?
For decades, the industry has incorporated the traditional 2D planar gate structure in designs, but planar is running out of gas due to the so-called short-channel effect. So, the industry is moving to finFETs, in which the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

In 2011, Intel was the first chipmaker to put finFETs into production. Initially rolled out at 22nm, Intel’s tri-gate transistor provides up to a 37% performance increase at low voltages, as compared to its 32nm planar transistors.

Now, Intel is ramping up its next-generation, 14nm finFET process. Intel’s chips based on this process are expected to roll out in the second half of the year, which is one or two quarters later than expected. And for the foundries, the transition from planar transistors at 28nm/20nm to finFETs could be a long and bumpy road.

“In general, finFETs bring a lot of challenges,” said Bradley Howard, vice president of the Etch Advanced Technology unit at Applied Materials. “Now, the industry is going to a very different device structure, where you have these fins standing up and a gate that wraps around it. So, it’s really not a big surprise that it will take some time to work through the issues. The reality is you have a lot of really smart people at TSMC, Samsung, GlobalFoundries or wherever. They will work through it and they will get it.”

Patterning challenges
One of the biggest challenges in the fab is patterning. Lithography, the process of printing patterns on a wafer, is a zero defect game with tight requirements. By 10nm, chipmakers would like to insert extreme ultraviolet (EUV) lithography to reduce the number of process steps and improve pattern fidelity. But EUV will likely miss the 10nm node due to ongoing issues with the power source.

So, chipmakers must extend 193nm immersion to 10nm, with the help of multiple patterning techniques. “With double patterning or multiple patterning, the designer needs to do color assignments to lay out the polygons,” said Cliff Hou, vice president of research and development at TSMC. “This kind of new environment will change the existing design practices. That will be a new challenge to our current design environment and the EDA tools.”

With 193nm immersion and multiple patterning, chipmakers have demonstrated the ability to print 11.8nm half-pitch gratings. “We know that imaging can be done there, but it’s the overlay that people want to ask us about,” said Martin McCallum, technical program manager at Nikon. “It’s also focus performance. And is it affordable?”

In multiple patterning, there are also several technology options, such as the traditional multiple exposure schemes, self-aligned double/quadruple patterning (SADP/SAQP), and directed self-assembly (DSA). “Self-aligned multiple patterning can actually solve our problems, but it does add complexity to the issue. Where is the complexity difference? The answer is we have more variations for the new nodes,” said Akihisa Sekiguchi, corporate vice president and deputy general manager of Tokyo Electron Ltd. (TEL).

“In the past, you’re variability was determined by a single shot. You worry about the CDU, overlay and line-edge roughness. In order to deliver today’s technology, you must also worry about the second, third and fourth (layers) and overlay. Each layer may add a slight error in terms of edge placement error. It’s a headache going forward,” Sekiguchi said.

Etch challenges
Etch, the art of removing materials to help shape the design, is another challenging process, especially as chipmakers migrate to finFETs. In bulk finFET production, the hard part is to make fins with consistent heights during the etch process. Imprecise fin patterning could cause variations.

In spacer etch, the trick is to remove the material from the fin sidewall, but retain it on the gate sidewall. Intel, for one, devised “tapered fins” to get around the problem. Proponents of the rival “rectangular fin” camp can do this by using over etching techniques, but this could also lead to fin and oxide erosion, according to experts.

“Apart from being a new device structure that has to get implemented, (finFETs have some) topography challenges,” Applied’s Howard said. “The topography drives an over etch. And if over etch is used to clear over more topographies, you are exposing your device to potentially more damage.”

To address the fin patterning problem, the industry is looking at a next-generation etch technology called atomic layer etch (ALE). ALE selectively and precisely removes materials one monolayer at a time. “ALE can create atomically smooth surfaces with good compositional control,” said Thorsten Lill, vice president of emerging technologies and the Systems Group at Lam Research.

Backend blues
Another concern for chipmakers is the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.

“There are big concerns,” said Daniel Edelstein, an IBM fellow and manager of BEOL technology strategy at IBM. “Scaling causes line resistance, or resistance per unit length, to blow up, simply by quadratic scaling of the wire cross-sectional area.”

In the interconnect flow, there are three main parts—metallization; low-k dielectrics; and the capping layer. In the metallization step, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

Then, a thin barrier layer of tantalum (Ta) and tantalum nitride (TaN) materials is deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper seed barrier via PVD. And finally, the structure is electroplated with copper.

“In the 130nm node and above, designers were able to get around some manufacturing limitations by building in redundancy for the design itself. So, they would have a lot more single vias. This would allow them to bridge any marginalities if you had some voiding along those lines or some imperfections in terms of the fill characteristics,” said Kavita Shah, global product manager at Applied Materials. “But when we go down to 20nm, we are just running out of room. There is no way to build any redundancy from the design aspect. What this means is that even if a few of these structures are not filled properly, the yield impact starts to become pretty dramatic.”

At 20nm and beyond, the industry will need to make changes in the flow. “In today’s interconnects, we start to see other challenges, such as high current densities. As this current density goes up, other secondary electrical effects start to dominate,” Shah said. “In order to address the electrical aspects of interconnect technology, we are beginning to see the need for new materials.”

In fact, Applied has rolled out a tool that brings cobalt as well as traditional materials into the flow. Applied’s tool makes use of its existing Endura platform. Using chemical vapor deposition (CVD), cobalt is used for the liner instead of Ta. Cobalt is also used for the capping layer. TaN is still utilized for the barrier using PVD. “The idea of using a cobalt liner layer is to promote continuity for the copper seed,” Shah said. “Improving the fill reliability using cobalt liners basically translates into better yield.”

Metrology/inspection issues
The unsung part of the flow is process control, which involves inspection and metrology. Metrology, the science of measuring and characterizing tiny structures and materials, is critical for the early stages of the yield ramp. For finFETs, however, there is no single metrology tool that can handle all of the 12 or more measurements of a finFET in three dimensions.

So, to address the problem, chipmakers are using a mix-and-match approach with today’s metrology tools. “To be honest, I think we are solving aspects of (the metrology challenges), but the problems are still there,” said John Allgair, director of product development at Nanometrics.

Despite the challenges in the fab, chipmakers are still moving full speed ahead with finFETs. “FinFETs remain a big challenge,” said Semico’s Itow, “but the industry will get through it pretty quickly.”