The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks

As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe.

Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect layers.

One emerging innovation in the semiconductor industry is the development of backside power delivery networks (BSPDNs). This architecture offers an alternative to traditional frontside power delivery networks (FSPDNs).

The BSPDN approach involves routing power lines through the backside of the wafer. This frees up the frontside for signal routing and active device regions.

A comparison of frontside versus backside power structures. Backside power delivery networks benefits include reduced power delivery noise, improved power integrity, and enhanced thermal management.

Advantages of BSPDN

This method provides a few advantages, such as reduced power delivery noise, improved power integrity, and enhanced thermal management.^1,2

• By decoupling the power and signal routing, BSPDNs can reduce the voltage drop and power supply noise, leading to a more stable and reliable device operation.³
• Additionally, the backside approach can alleviate congestion on the frontside metal layers, allowing for more efficient use of the available routing resources and enabling higher device densities.⁴

Challenges of implementing BSPDN

There are challenges associated with the implementation of BSPDNs. One of the primary challenges is the increased complexity in the fabrication process. The integration of BSPDNs requires additional steps such as wafer thinning, backside metallization, and through-silicon via (TSV) formation.⁵ These processes result in new challenges in terms of wafer handling, alignment precision, and thermal budget management.

• Wafer thinning, for instance, can lead to mechanical fragility and increased susceptibility to warping and breakage.⁶
• The formation of TSVs, which are essential for establishing electrical connections between the frontside and backside, demands precise etching and filling techniques to ensure reliability and performance.^5,7

Further, the introduction of backside metallization layers can also cause thermal and mechanical stress, which can impact overall device integrity.^6,8 Stress management is a critical aspect of semiconductor device performance, particularly in advanced transistor architectures such as gate-all-around (GAA) transistors.

Stress can influence carrier mobility, threshold voltage, and overall device reliability.^9,10 In the context of BSPDNs, the additional processing steps and material layers can introduce new sources of stress. For example, the thermal expansion mismatch between different materials used in the backside metallization and TSVs can generate mechanical stress, potentially affecting the active regions of the device.^7,11

The backside integration approach can impact the stress distribution within the active device, potentially leading to variations in electrical characteristics.^9,10 For instance, the mechanical stress induced by the backside metallization and TSVs can influence the channel strain in GAA transistors, which affects carrier mobility and drive current.

There is a need to understand and mitigate these stress effects to ensure optimal device performance.

Analyzing differing stress levels in GAA

The Semiverse Solutions team performed an analysis of stress evolution that occurs during frontside and backside fabrication steps of nanosheet channels in GAA transistors. Using virtual fabrication techniques,¹² we investigated stress variations and developed a comparative evaluation of different integration approaches for backside and frontside source/drain (S/D) contacts.

In our study, we investigated a frontside connect scheme and two backside connect schemes, which included a direct backside connect (DBC) and a self-aligned backside connect (SABC) scheme. For each scheme, we studied the impact of S/D epitaxial silicon germanium (SiGe) on nanosheets only versus epitaxial SiGe on both nanosheets and substrate (figure 1).

Fig. 1: A frontside connect scheme (a, d) and two backside connect schemes that included a direct backside connect (c, f) and a self-aligned backside connect scheme (b, e). For each scheme, the Lam team studied the impact of S/D epitaxial silicon germanium (SiGe) on nanosheets only (a, b, c) versus epitaxial SiGe on both nanosheets and substrate (d, e, f). (Image from “Stress Evolution Analysis of Gate-All-Around Transistors: Frontside and Backside Integration Approaches”¹⁴)

Our results indicated stress in the X and Z directions, along with the Z displacement, were substantially different for the backside connect scheme compared to the frontside connect scheme.

Fig. 2: (a) Fabrication process steps for the SABC scheme for the epi-on-nanosheet-only case. (b-d) Variations in the stress tensor’s xx, zz components (σ_xx, σ_zz) and vertical displacement in arbitrary units as measured at the center of the channel through the key fabrication steps of the transistor. (e) The directions of the xx and zz stress components. (f-g) The vertical displacement of the GAA nanosheets as measured using virtual fabrication software. The top nanosheet has a higher displacement than the one at the bottom. (f) As seen in the model from a side (g) plot of z-displacement versus channel location. (Image from “Stress Evolution Analysis of Gate-All-Around Transistors: Frontside and Backside Integration Approaches”¹⁴)

Notably, while stress in the X direction decreases between the epitaxial (EPI) growth and channel release steps, the stress in the Z dimension increases. The Z displacement increases significantly during the backside Si recess step. Additionally, switching from an EPI on both nanosheet and substrate to EPI on nanosheet-only scheme does not alter the stress profile for the backside connect scheme. However, for the frontside connect scheme, this switch results in significant changes in the stress profile.

We also researched the impact of the Ge fraction (x) in sacrificial Si1-xGex on the channel stress for these integration schemes.

This study underscores the significant impact of different integration schemes on channel stress and nanosheet vertical displacement in semiconductor fabrication. It demonstrates that backside connect integration schemes can generate greater mechanical device stress when compared to frontside connect schemes.

We also showed that it is possible to have the advantages of a self-aligned backside connect scheme without a significant penalty in stress profile. This work provides critical insight into the impact of different BSPDN process integration schemes on device stress and offers valuable guidance in the development of future semiconductor devices using backside power delivery networks.

To learn more about this study, please read the full publication, “Stress Evolution Analysis of Gate-All-Around Transistors: Frontside and Backside Integration Approaches.”¹⁴

References

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