The Road Ahead for 2014: Semiconductors

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related to design, verification and implementation tools.

There is a large amount of agreement in the industry about the macro trends for semiconductors this year. They fall into three main categories:

• Migration to new processing nodes.
• Adoption of FinFETs.
• Increasing utilization of 2.5D and 3D integration.

When we couple these with the general market trends, there could be significant changes ahead for the industry.

“Wall Street has come to see all innovation in the semiconductor industry in terms of feature size, but Moore-stress and rapidly increasing cost with diminishing returns may bring a welcome shift to focus on content—what devices can do and who provides those applications, rather than the enabling technology,” says Bernard Murphy, chief technology officer at Atrenta.

At least part of the blame for those diminishing returns are increasing technical issues involving and materials. “We expect ongoing delays in implementing EUV, as well as escalating process complexity to continue to challenge IC scaling,” adds David Fried, chief technology officer at Coventor.

That, coupled with increased complexity, is driving up the cost from design through manufacturing. “The mobile market will continue to be dominated by a handful of chip manufacturers such as Intel, Mediatek, Qualcomm and Samsung,” explains a spokesperson from Ansys-Apache, “that can afford to make the investment and have the core expertise to move to 10nm process technology needed to remain competitive in this market.”

And that is the key to it. The investment necessary to move to each new node is increasing to the point where fewer and fewer applications can justify it and a decreasing number of fabs can afford to develop and deploy the new processes. But the and other emerging trends may not need these advanced process nodes, instead being able to survive and thrive on existing technologies. Because of this, there is some disagreement about the rate at which these new nodes will see adoption.

“Over the last year, the major foundry ecosystems largely moved from alpha or beta (v0.x) versions of their 16/14nm design rule decks and PDKs to versions more suitable for production (e.g., v1.x),” says Joseph Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor Graphics. “Fabless customers are just beginning to implement their first test chip tape-outs for 16nm/14nm, and 2014 will see most of the 20nm early-adopter customers also preparing their first 16nm/14nm test chips.”

For others, hanging back a node is looking increasingly attractive. “28-nm will remain a dominant node for chipsets going into cost-effective smartphones” says John Koeter, vice president of marketing for the Solutions Group at Synopsys.

Adding to the complexity at 16/14nm is the adoption of FinFETs. “FinFETs will initiate production in leading foundries in the second half of the year,” says Dave Lazovsky, president and CEO, Intermolecular. “These lower off-state leakage 3D transistors represent significant changes in architecture and gate stack process integration and will have a bigger impact on performance per dollar per watt than anything since the introduction of high-k/metal gate transistors.”

But new technologies also create new hurdles. “FinFET is a revolutionary change to device fabrication and modeling, requiring a more complex SPICE model and challenging the existing circuit behavior ‘rules of thumb’ on which experienced designers have relied for years with planar devices,” says Ravi Subramanian, president and CEO of Berkeley Design Automation.

In addition, there is still uncertainty about the best substrate material for the production of FinFETs and questions about whether SOI technology will extend the life of planar transistors for another node. The impact of FinFETs also moves into the area of memory design and fabrication.

“In memory applications, FinFET technology will continue to drive change and challenge the status quo of “relaxed accuracy” simulation for IP characterization,” says Subramanian. “Design teams are realizing that it is no longer acceptable to tolerate 2% to 5% inaccuracy in memory IP characterization. Designers will need to perform an increased amount of intelligent, efficient, and effective circuit characterization at the block level and at the project level to ensure that their designs meet rigorous requirements prior to silicon.”

Memory changes
“2014 will be the year that NAND Flash transitions to 3D NAND in volume production,” predicts Lazovsky. “This is an important milestone and precursor to more advanced NVM technology, like 3D ReRAM, which we expect to see progressing steadily toward high-volume production over the next few years. In DRAM, we expect 20nm devices will be qualified by all three leading manufacturers and moved into production in the second half of the year, with 1X DRAM technology likely qualified by at least one player by the end of 2014.”

The outlook for memory in general looks positive. “The strong expansion of the DRAM and NAND flash memory markets, (rising 35% and 28% respectively in 2013) will be duplicated in 2014,” predicts Graham Bell, vice president of marketing at Real Intent. “In August we saw Samsung begin mass producing the industry’s first 3D Vertical NAND flash memory, which breaks through the current scaling limit for existing NAND flash technology. The 128Gb part uses a ‘skyscraper’ of NAND cells with charge-trap technology. What is impressive are the 24 layers used for the gate stacking in this 2xnm-class process. More companies will attempt to leap across the 3D technology gap to achieve this next-generation scaling in 2014.”

And the migration to 2.5D and 3D technology was a common thread in many people’s predictions. “2.5D packaging technology will start to see the light of day in more applications,” says Mike Gianfagna, vice president of marketing at eSilicon. “Watch specifically what happens with interposer design. There will be exciting innovations there. Traction for 2.5D will release everyone from the need to put the entire new design on one advanced silicon substrate, so design starts will begin going up as a result.”

But getting there is not a slam dunk, either. “We’ll need 3D packaging implementations that are an order of magnitude cheaper than current offerings,” says Sawicki.

When that does happen, there are plenty of more-than-Moore applications waiting to make use of it. “Once we move from data to actually interacting with the real world,” continues Sawicki, “analog/mixed signal, MEMS and other sensors role in the semiconductor solution will become much greater.”

The IP industry is getting ready for these changes. “Imagination is already working closely with leading foundries to investigate how the characteristics of their latest processes, such as 16FinFET and 3D-ICs, influence the design of high performance IP-based SoCs,” explains Amit Rohatgi, vice president of strategic marketing at Imagination Technologies. “The semiconductor industry needs to develop and promote new technologies and standards that enable more performance and features within a balanced power envelope.”

But not everything is ready for integration yet. Koeter has a sobering prediction for silicon photonics “Optical interconnect is not likely to happen in 2014 as integrated drivers/transceivers are not yet possible in CMOS.”

Even before the latest news related to Intel mothballing its latest fab, , president and CEO of OneSpin Solutions, said “it is worth watching the opening of the Intel facilities to other companies and the new platforms introduced as a result.” Maybe that will is not happening fast enough for Intel.

As the industry continues to experiment with the new production nodes, Coventor’s Fried believes there is a better way. “2014 will be the year where foundries, IDMs and memory manufacturers demonstrate the time-to-market advantage of developing their advanced technologies using virtual fabrication.”