The Week In Review: Design

IP
Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager.

ARM rolled out additions to its enterprise-class SoC interconnects for quad-core processor clusters in small cell base stations, and 48-core heterogeneous compute solutions with a mix of CPUs and DSPs for macro cell base states, core networks and servers.

Tools
Cadence rolled out a functional safety verification solution for the automotive market, which it said reduces ISO 26262 compliance prep by up to 50%.

Numbers
Cadence reported solid Q3 numbers. Revenue was $400 million, up from $367 million in Q3 2013. Net income was $80 million, compared with $63 million in the same period in 2013.

ARM reported strong Q3 numbers, as well. Revenue was $320.2 million, up from $286 million in Q3 2013. Earnings per share was $16.93, up from $15.30 in 2013. Of its processor unit shipments during the quarter, ARM7 accounted for 26%, ARM9 14%, and Cortex-M 34%. That was reflected in the unit shipments for mobile market, 40%; enterprise 17%; home 5%; and embedded 38%.

Rambus reported its quarterly results. Revenue was $69.7 million down 5% from $71.0 million in Q3 2013 due to lower royalty revenue from Samsung and Nvidia. Net income was $5.5 million, compared to a $5.7 million loss in 2013. On a non-GAAP basis, net income was $14.8 million, down from $18.9 million.

NXP reported healthy Q3 results, too. Revenue was $1.515 billion, up 21% from the previous year’s $1.213 billion. Net income was $121 million, which included a $213 million charge, compared with $159 million in 2013. On a non-GAAP basis, net income was $334 million, up from $219 million in 2013.

Deals/certifications
Sonics will use Magillem‘s IP-XACT validation tools to improve integration of its NoC IP in heterogeneous, multi-core devices.

SMIC certified Synopsys‘ physical verification signoff tool for its 28nm process.

Atrenta won a deal with Kodak Alaris, which will use its CDC analysis tools for FPGA design and verification.

NXP won a deal with Google, which will support its security keys for secure sign-in.

Synopsys also won a deal with Marvell, which used its memory system multi-memory bus processor for embedded test and repair to reduce its SoC die size by 10%. And it won a deal with VIA Technologies, which says it cut silicon test time by 11X using Synopsys’ test compression tool.

Cadence won a deal with Global Unichip, which is using its digital implementation flow for 16FF+ designs. Global Unichip reported a 2X system performance improvement and an 18% frequency increase.

People
Mentor Graphics appointed A.J. Incorvaia as vice president and general manager of the company’s Board Systems Division.

Events
Cadence will host a Mixed Signal Technology Summit on Oct. 28 at its San Jose headquarters in Building 10.

Si2 will sponsor a new conference called 3D Architectures for Semiconductor Integration and Packaging, to be held Dec. 10-12 at the Hyatt Regency San Francisco Airport in Burlingame, California.