Week In Review: Design, Low Power

Tools & IP
Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and double precision [D] instructions; a data cache with configurable size, associativity, and cache lines that can be configured with either AXI or AHB-Lite interfaces; and additional instructions for bit manipulation which can be beneficial for error detection/correction, DSP, and security algorithms.

Mixel, Rambus, and Hardent teamed up on an integrated MIPI DSI-2 display subsystem. Including MIPI C-PHY/D-PHY combo, DSI-2 digital controller, and VESA Display Stream Compression (DSC). Targeting mobile, AR/VR and automotive displays, the integrated subsystem is fully verified and is available in both host (TX) and peripheral (RX) versions.

Tortuga Logic is developing a Security Governance Platform (SGP) that expands its Radix tool for hardware vulnerability detection and mitigation. The SGP expands the security testing process to enable teams such as engineering, security, marketing, and legal/compliance to collaboratively manage a rigorous security program spanning the entire product development lifecycle from security requirement management and regular security testing to security signoff before shipping to manufacturing. A recent investment from not-for-profit national security venture capital firm In-Q-Tel is funding the effort.

Market research firm IC Insights is raising its forecast for 2021, now expecting the IC market to grow 19%, which is noted as a conservative figure. The 19% market growth is forecast to be driven by a 17% surge in IC unit volume shipments and a 1% increase in IC ASP this year.

Deals
Kyocera Document Solutions used Synopsys’ DesignWare ARC EV6x Embedded Vision Processor IP with convolutional neural network (CNN) engine and ARC MetaWare EV Development Toolkit in its new multifunction product (MFP) SoC with first-pass silicon success. Additionally, Kyocera deployed Synopsys’ HAPS FPGA-based prototyping system to accelerate ARC EV software development, SoC integration, and system validation.

SiPearl is using Siemens EDA’s Veloce hardware emulation platform in the verification of its Rhea high-performance, low-power microprocessor being developed for the European exascale supercomputer project, citing fast compilation, full design visibility, low cost of ownership. The company plans to allow its future clients to access the platform to carry out multi-scale performance tests with Rhea for their applications in fields including fluid dynamics, climatology, medical research, geo-sciences, and artificial intelligence. SiPearl anticipates a launch in 2022.

ENGIE Lab CRIGEN is utilizing Ansys’ digital twin solution to build twins of industrial equipment to boost product reliability and evaluate new concepts in energy production, as well as enable engineers to control industrial processes, anticipate carbon reduction challenges, and lower maintenance costs of in-service equipment.

Research projects
OpenHW Group and Mitacs launched OpenHW Accelerate, a $22.5M multi-year co-funded research program to drive research in next generation of class-leading open-source processors, architectures and support software for embedded AI and machine learning applications, among other future energy-intensive computing requirements.

The first OpenHW Accelerate project, CORE-V VEC, is an effort to explore architectural optimizations for RISC-V vector processor implementations used in high-throughput multidimensional sensor data processing and ML acceleration at the edge. The three-year, joint-research collaboration between Polytechnique Montréal and ETH Zürich is sponsored by CMC Microsystems. More projects will be announced in the coming months.

DARPA announced teams for its Data Protection in Virtual Environments (DPRIVE) program. The program aims to develop an accelerator for fully homomorphic encryption (FHE), a major data privacy and security ideal that would enable computing on encrypted data. However, processing data using FHE methods is data intensive and inefficient on even simple operations.

Four teams of researchers will be led by Duality Technologies, Galois, SRI International, and Intel. According to DARPA, “Each team will develop an FHE accelerator hardware and software stack that reduces the computational overhead required to make FHE calculations to a speed comparable to similar unencrypted data operations. The teams will create accelerator architectures that are flexible, scalable, and programmable, but will also explore various approaches with different native word sizes.” The teams will also try out different approaches to memory management, flexible data structures and programming models, and formal verification methods to ensure the FHE implementation is correct-by-design.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The Silicon Valley Women in Engineering Conference will be held Mar. 20. IRPS 2021: International Reliability Physics Symposium will be held Mar. 21-24, and the tinyML Summit: Enabling Ultra-low Power Machine Learning At The Edge will take place Mar. 22-26. The Leti Photonics Workshop will happen on Mar. 25 with multiple times available. The U.S. government-focused electronics conference GOMACTech will be held Mar. 29-Apr. 1.